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Accelerating FPGA Debug: Increasing Visibility Using a Runtime reconfigurable Observation and Triggering Network

acm transactions ON DESIGN AUTOMATION OF ELECTRONIC systems 2014年第2期19卷 14-14页

作者： Hung, Eddie Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada

FPGA technology is commonly used to prototype new digital designs before entering fabrication. Whilst these physical prototypes can operate many orders of magnitude faster than through a logic simulator, a fundamental limitation is their lack of on-chip visibility when debugging. To counter this, trace-buffer-based instrumentation can be installed into the prototype, allowing designers to capture a predetermined window of signal data during live operation for offline analysis. However, instead of requiring the designer to recompile their entire circuit every time the window is modified, this article proposes that an overlay network is constructed using only spare FPGA routing multiplexers to connect all circuit signals through to the trace instruments. Thus, during debugging, designers would only need to reconfigure this network instead of finding a new place-and-route solution. Furthermore, we describe how this network can deliver signals to both the trigger and trace units of these instruments, which are implemented simultaneously using dual-port RAMs. Our results show that new network configurations connecting any subset of signals to 80-90% of the available RAM capacity can be computed in less than 70 seconds, for a 100,000 LUT circuit, as many times as necessary. Our tool-QuickTrace-is available for download.

关键词： Algorithms Design Verification FPGA debug FPGA prototyping verification trace buffers overlay network

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A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in reconfigurable systems

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acm transactions on reconfigurable technology and systems 2014年第2期7卷 15-15页

作者： Niu, Xinyu Jin, Qiwei Luk, Wayne Weston, Stephen Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England Maxeler Technol London England

Finite-difference methods are computationally intensive and required by many applications. Parameters of a finite-difference algorithm, such as grid size, can be varied to generate design space which contains algorithm instances with different constant coefficients. An algorithm instance with specific coefficients can either be mapped into general operators to construct static designs, or be implemented as constant-specific operators to form dynamic designs, which require runtime reconfiguration to update algorithm coefficients. This article proposes a tuning method to explore the design space to optimise both the static and the dynamic designs, and an evaluation method to select the design with maximum overall throughput, based on algorithm characteristics, design properties, available resources and runtime data size. For benchmark applications option pricing and Reverse-Time Migration (RTM), over 50% reduction in resource consumption has been achieved for both static designs and dynamic designs, while meeting precision requirements. For a single hardware implementation, the RTM design optimised with the proposed approach is expected to run 1.8 times faster than the best published design. The tuned static designs run thousands of times faster than the dynamic designs for algorithms with small data size, while the tuned dynamic designs achieve up to 5.9 times speedup over the corresponding static designs for large-scale finite-difference algorithms.

关键词： Algorithm tuning finite-difference methods reconfigurable computing

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The iDEA DSP Block-Based Soft Processor for FPGAs

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acm transactions on reconfigurable technology and systems 2014年第3期7卷 19-19页

作者： Cheah, Hui Yan Brosser, Fredrik Fahmy, Suhaib A. Maskell, Douglas L. Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

DSP blocks in modern FPGAs can be Used for a wide range of arithmetic functions, offering increased performance while saving logic resources for other uses. They have evolved to better support a plethora of signal processing tasks, meaning that in other application domains they may be underutilised. The DSP48E1 primitives in new Xilinx devices support dynamic programmability that can help extend their usefulness;the specific function of h DSP block can be modified on a cycle-by-cycle basis. However, the standard, synthesis flow does not leverage this flexibility in the vast majority of cases. The lean DSP Extension Architecture (iDEA) presented in this article builds around the dynamic programmability of a single DSP48E1 primitive, with minimal additional logic to create a general-purpose processor supporting a full instruction-set architecture. The result is a very compact, fast processor that can execute a full gamut of general machine instructions. We show a number of simple applications compiled using an MIPS compiler and translated to the iDEA instruction set, comparing with a Xilinx MicroBlaze to show estimated performance figures. Being based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, Virtex-7, and Zynq families.

关键词： Design Algorithms Performance Field programmable gate arrays reconfigurable computing soft processors

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MORPHEUS: A Heterogeneous Dynamically reconfigurable Platform for Designing Highly Complex Embedded systems

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acm transactions ON EMBEDDED COMPUTING systems 2013年第3期12卷 1-33页

作者： Voros, Nikolaos S. Hubner, Michael Becker, Juergen Kuhnle, Matthias Thomaitiv, Florian Grasset, Arnaud Brelet, Paul Bonnot, Philippe Campi, Fabio Schuler, Eberhard Sahlbach, Henning Whitty, Sean Ernst, Rolf Billich, Enrico Tischendorf, Claudia Heinkel, Ulrich Ieromnimon, Frank Kritharidis, Dimitrios Schneider, Axel Knaeblein, Joachim Putzke-Roming, Wolfram Univ Karlsruhe TII Karlsruhe Germany Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Alcatel Lucent Murray Hill NJ USA

Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that respect, this paper introduces an innovative technology platform, called MORPHEUS, which intents to provide complete design framework for dealing with the aforementioned challenges. MORPHEUS consists of a state of the art architecture that encompasses heterogeneous reconfigurable accelerators for implementing on the same hardware architecture applications with varying characteristics and a tool chain that, through a software oriented approach, eases the implementation of highly complex applications with heterogeneous characteristics. The proposed approach has been tested and evaluated through state of the art cases studies borrowed from complementary application domains.

关键词： Algorithms Design Experimentation Performance Verification

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Virtualizable hardware/software design infrastructure for dynamically partially reconfigurable systems

Virtualizable hardware/software design infrastructure for dy...

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作者： Huang, Chun-Hsian Hsiung, Pao-Ann Department of Computer Science and Information Engineering National Taitung University Taitung Taiwan Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan

In most existing works, reconfigurable hardware modules are still managed as conventional hardware devices. Further, the software reconfiguration overhead incurred by loading corresponding device drivers into the kernel of an operating system has been overlooked until now. As a result, the enhancement of system performance and the utilization of reconfigurable hardware modules are still quite limited. This work proposes a virtualizable hardware/software design infrastructure (VDI) for dynamically partially reconfigurable systems. Besides the gate-level hardware virtualization provided by the partial reconfiguration technology, VDI supports the device-level hardware virtualization. In VDI, a reconfigurable hardware module can be virtualized such that it can be accessed efficiently by multiple applications in an interleaving way. A Hot-Plugin Connector (HPC) replaces the conventional device driver, such that it not only assists the device-level hardware virtualization but can also be reused across differen hardware modules. To facilitate hardware/software communication and to enhance system scalability, the proposed VDI is realized as a hierarchical design framework. User-designed reconfigurable hardware modules can be easily integrated into VDI, and are then executed as hardware tasks in an operating system for reconfigurable systems (OS4RS). A dynamically partially reconfigurable network security system was designed using VDI, which demonstrated a higher utilization of reconfigurable hardware modules and a reduction by up to 12.83% of the processing time required by using the conventional method in a dynamically partially reconfigurable system. © 2013 acm.

关键词： reconfigurable hardware

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Using Memory Profile Analysis for Automatic Synthesis of Pointers Code

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acm transactions ON EMBEDDED COMPUTING systems 2013年第3期12卷 1-21页

作者： Ben-Asher, Yosi Rotem, Nadav Univ Haifa IL-31999 Haifa Israel

One of the main advantages of high-level synthesis (HLS) is the ability to synthesize circuits that can access multiple memory banks in parallel. Current HLS systems synthesize parallel memory references based on explicit array declarations in the source code. We consider the need to synthesize not only array references but also memory operations targeting pointers and dynamic data structures. This paper describes Automatic Memory Partitioning, a method for automatically synthesizing general data structures (arrays and pointers) into multiple memory banks for increased parallelism and performance. We use source code instrumentation to collect memory traces in order to detect linear memory access patterns. The memory traces are used to split data structures into disjoint memory regions and determine which segments may benefit from parallel memory access. We present an algorithm for allocating memory segments into multiple memory banks. Experiments show significant improvements in performance while conserving the number of memory banks.

关键词： Design Algorithms Performance reconfigurable computing memory analysis memory banks

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Heuristic search for adaptive, defect-tolerant multiprocessor arrays

Heuristic search for adaptive, defect-tolerant multiprocesso...

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transactions on Embedded Computing systems

作者： Vasilikos, Vasileios Smaragdos, Georgios Strydis, Christos Sourdis, Ioannis Delft University of Technology Netherlands Erasmus University Medical Center Netherlands Chalmers University of Technology Sweden

In this article, new heuristic-search methods and algorithms are presented for enabling highly efficient and adaptive, defect-tolerant multiprocessor arrays. We consider systems where a homogeneous multiprocessor array lies on top of reconfigurable interconnects which allow the pipeline stages of the processors to be connected in all possible configurations. Considering the multiprocessor array partitioned in substitutable units at the granularity of pipeline stages, we employ a variety of heuristic-search methods and algorithms to isolate and replace defective units. The proposed heuristics are designed for off-line execution and aim at minimizing the performance overhead necessarily introduced to the array by the interconnects' latency. An empirical evaluation of the designed algorithms is then carried out, in order to assess the targeted problem and the efficacy of our approach. Our findings indicate this to be a NP-complete computational problem, however, our heuristic-search methods can achieve, for the problem sizes we exhaustively searched, 100% accuracy in finding the optimal solution among 1019 possible candidates within 2.5 seconds. Alternatively, they can provide near-optimal solutions at an accuracy which consistently exceeds 70% (compared to the optimal solution) in only 10-4 seconds. © 2013 acm.

关键词： Heuristic methods Heuristic algorithms Modular robots Optimal systems Optimization Pipeline processing systems Pipelines Adaptable architecture Empirical evaluations Heuristic search methods Interconnection architecture Near optimal solutions Parallel processor Pipeline processor reconfigurable interconnects

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QUKU: A dual-layer reconfigurable architecture

QUKU: A dual-layer reconfigurable architecture

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作者： Bergmann, Neil W. Shukla, Sunil K. Becker, Jurgen School of ITEE University of Queensland st Lucia Brisbane 4072 Australia IBM TJ Watson Research Center Hawthorne NY 10532 United States ITIV Karlsruhe Institute of Technology 76131 Karlsruhe Germany

A new architecture, QUKU, is proposed for implementing stream-based algorithms on FPGAs, which combines the advantages of FPGA and Coarse Grain reconfigurable Arrays (CGRAs). QUKU consists of a dynamically reconfigurable, coarse-grain Processing Element (PE) array with an associated softcore processor providing system support. At a coarse-grain, the PE array can be reconfigured on a cycle-by-cycle basis to change the PE functionality similarly to that in a conventional CGRA. At a fine-grain, the whole FPGA can be reconfigured statically to implement a completely different PE array that serves the target application in a better way. Advantages of the fine-grain reconfiguration include individually customized PEs, adaptable numeric format support and customizable interconnect network. A prototype CAD tool framework is also developed which facilitates programming the QUKU architecture. An example application consisting of two different image detectors is implemented to demonstrate the advantages of QUKU. QUKU provides up to 140 times speedup and 40 times improvement in area-time product compared to an implementation running on an FPGA-based softcore. The area-time product for QUKU is around 16% lower than that of a custom circuit based implementation on the same FPGA. The per-PE customization provides an area-time saving of approximately 31% compared to a homogeneous 4 × 4 array of PEs for the same application. The experimental results demonstrate that a dual layered reconfigurable architecture provides significant potential benefits in terms of flexibility, area and processing efficiency over existing reconfigurable computing architectures for DSP. © 2013 acm.

关键词： Field programmable gate arrays (FPGA)

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Introduction to the Special Section on 19th reconfigurable Architectures Workshop (RAW 2012)

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acm transactions on reconfigurable technology and systems 2013年第2期6卷 6-6页

作者： Goehringer, Diana Cumplido, Rene Ruhr Univ Bochum Bochum Germany Natl Inst Astrophys Opt & Elect Mexico City DF Mexico

The execution runtime usually is a headache for designers performing application mapping onto reconfigurable architectures. In this article we propose a methodology, as well as the supporting toolset, targeting to provide fast application implementation onto reconfigurable architectures with the usage of a Just-In-Time (JIT) compilation framework. Experimental results prove the efficiency of the introduced framework, as we reduce the execution runtime compared to the state-of-the-art approach on average by 53.5×. Additionally, the derived solutions achieve higher operation frequencies by 1.17×, while they also exhibit significant lower fragmentation ratios of hardware resources.

关键词： Workshops Shanghai China workshops reconfigurable architectures

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A reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator

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acm transactions on reconfigurable technology and systems 2013年第4期6卷 17-17页

作者： Ananthan, T. Vaidyan, M. V. Natl Inst Technol Calicut Calicut 673601 Kerala India

The self-tuning regulator (STR) is a popular adaptive control algorithm. A high-performance computer is required for its implementation due to the heavy online computational burden. To extend STR for more real-time applications, a parallel hardware implementation on a low-cost reconfigurable computer is presented. The hardware was incorporated with multistage matrix multiplication (MMM) and trace technique to enhance the processing speed. This design was deeply pipelined to achieve high throughput. The algorithm was prototyped on a Xilinx field-programmable gate array (FPGA) device with a maximum operating frequency of 210.436 MHz. Application-specific integrated circuit (ASIC) implementation of STR was reported.

关键词： Algorithms Design Performance Adaptive control self-tuning regulator parallel hardware reconfigurable computer ASIC FPGA

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