检索结果-内蒙古大学图书馆

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control

acm transactions on reconfigurable technology and systems 2011年第2期4卷 15-15页

作者： Nakajima, Mao Watanabe, Minoru Shizuoka Univ Dept Elect & Elect Engn Hamamatsu Shizuoka 4328561 Japan

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

关键词： Design Experimentation Field programmable gate arrays holographic memory optically reconfigurable gate arrays

来源：评论

学校读者我要写书评

暂无评论

A Mapping-Scheduling Algorithm for Hardware Acceleration on reconfigurable Platforms

引用

acm transactions on reconfigurable technology and systems 2014年第2期7卷 9-9页

作者： Antonio Clemente, Juan Beretta, Ivan Rana, Vincenzo Atienza, David Sciuto, Donatella Univ Complutense Madrid Comp Architecture Dept E-28040 Madrid Spain Ecole Polytech Fed Lausanne ESL IEL STI EPFL CH-1015 Lausanne Switzerland Politecn Milan DEI I-20113 Milan Italy

reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involvemultiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

关键词： Mapping task scheduling reconfiguration overheads reconfigurable systems runtime reconfiguration

来源：评论

学校读者我要写书评

暂无评论

Molecular Dynamics Simulations on High-Performance reconfigurable Computing systems

引用

acm transactions on reconfigurable technology and systems 2010年第4期3卷 23-23页

作者： Chiu, Matt Herbordt, Martin C. Boston Univ Dept Elect & Comp Engn Comp Architecture & Automated Design Lab Boston MA 02215 USA

The acceleration of molecular dynamics (MD) simulations using high-performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore and GPUs, there is now a question whether MD on HPRC can be competitive. We concentrate here on the MD kernel computation: determining the short-range force between particle pairs. In one part of the study, we systematically explore the design space of the force pipeline with respect to arithmetic algorithm, arithmetic mode, precision, and various other optimizations. We examine simplifications and find that some have little effect on simulation quality. In the other part, we present the first FPGA study of the filtering of particle pairs with nearly zero mutual force, a standard optimization in MD codes. There are several innovations, including a novel partitioning of the particle space, and new methods for filtering and mapping work onto the pipelines. As a consequence, highly efficient filtering can be implemented with only a small fraction of the FPGA's resources. Overall, we find that, for an Altera Stratix-III EP3ES260, 8 force pipelines running at nearly 200 MHz can fit on the FPGA, and that they can perform at 95% efficiency. This results in an 80-fold per core speed-up for the short-range force, which is likely to make FPGAs highly competitive for MD.

关键词： Algorithms Design Performance FPGA-based coprocessors high performance reconfigurable computing bioinformatics biological sequence alignment application acceleration

来源：评论

学校读者我要写书评

暂无评论

Schedulability Analysis of Preemptive and Nonpreemptive EDF on Partial Runtime-reconfigurable FPGAs

引用

acm transactions ON DESIGN AUTOMATION OF ELECTRONIC systems 2008年第4期13卷 56-1--56-43-0页

作者： Guan, Nan Deng, Qingxu Gu, Zonghua Xu, Wenyao Yu, Ge Northeastern Univ Inst Comp Software Shenyang 110004 Peoples R China Hong Kong Univ Sci & Technol Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China Zhejiang Univ Coll Elect Engn Hangzhou 310027 Peoples R China

Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design, and Partial Runtime-reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this article, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bounds for several variants of global preemptive/nonpreemptive EDF scheduling, and compare the performance of different utilization bound tests.

关键词： FPGA Real-time scheduling reconfigurable devices

来源：评论

学校读者我要写书评

暂无评论

A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs

引用

acm transactions on reconfigurable technology and systems 2010年第2期3卷 6-6页

作者： Bodily, John Nelson, Brent Wei, Zhaoyi Lee, Dah-Jye Chase, Jeff Brigham Young Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing computations. Applications successfully implemented on FPGAs typically contain high levels of parallelism and often use simple statically scheduled control and modest arithmetic. Recently introduced computing devices such as coarse-grain reconfigurable arrays, multi-core processors, and graphical processing units promise to significantly change the computational landscape and take advantage of many of the same application characteristics that fit well on FPGAs. One real-time computing task, optical flow, is difficult to apply in robotic vision applications because of its high computational and data rate requirements, and so is a good candidate for implementation on FPGAs and other custom computing architectures. This article reports on a series of experiments mapping a collection of different algorithms onto both an FPGA and a GPU. For two different optical flow algorithms the GPU had better performance, while for a set of digital comm MIMO computations, they had similar performance. In all cases the FPGA implementations required 10x the development time. Finally, a discussion of the two technology's characteristics is given to show they achieve high performance in different ways.

关键词： Experimentation Design Performance Measurement Digital communications FPGA GPU optical flow reconfigurable computing

来源：评论

学校读者我要写书评

暂无评论

ReShape: Towards a High-Level Approach to Design and Operation of Modular reconfigurable systems

引用

acm transactions on reconfigurable technology and systems 2013年第1期6卷 5-5页

作者： Neely, Christopher E. Brebner, Gordon Shang, Weijia Xilinx Inc Xilinx Labs San Jose CA USA Santa Clara Univ Dept Comp Engn Santa Clara CA 95053 USA Santa Clara Univ Santa Clara CA 95053 USA

The latest FPGA devices provide the headroom to implement large-scale and complex systems. A key requirement is the integration of modules from diverse sources to promote modular design and reuse. A contrary factor is that using dynamic partial reconfiguration typically requires low-level planning of the system implementation. In this article, we introduce ReShape: a high-level approach for designing reconfigurable systems by interconnecting modules, which gives a "plug and play" look and feel, is supported by tools that carry out implementation functions, and is carried through to support system reconfiguration during operation. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules: for example, the streaming of data, or the reading and writing of data to and from memory modules. The details of wiring and signaling are hidden from view, via metadata associated with individual modules. This setting allows system reconfiguration at the module level, both by supporting type checking of replacement modules and by managing the overall system implementation, via metadata associated with its FPGA floorplan. The methodology and tools have been implemented in a prototype targeted to a domain-specific setting-high-speed networking-and have been validated on real telecommunications design projects.

关键词： Algorithms Design Languages Modular system design modular system reconfiguration high-level tools for FPGAs networking systems

来源：评论

学校读者我要写书评

暂无评论

Reconfiguration and Communication-Aware Task Scheduling for High-Performance reconfigurable Computing

引用

acm transactions on reconfigurable technology and systems 2010年第4期3卷 20-20页

作者： Huang, Miaoqing Narayana, Vikram K. Simmler, Harald Serres, Olivier El-Ghazawi, Tarek George Washington Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Ashburn VA 20147 USA

High-performance reconfigurable computing involves acceleration of significant portions of an application using reconfigurable hardware. When the hardware tasks of an application cannot simultaneously fit in an FPGA, the task graph needs to be partitioned and scheduled into multiple FPGA configurations, in a way that minimizes the total execution time. This article proposes the Reduced Data Movement Scheduling (RDMS) algorithm that aims to improve the overall performance of hardware tasks by taking into account the reconfiguration time, data dependency between tasks, intertask communication as well as task resource utilization. The proposed algorithm uses the dynamic programming method. A mathematical analysis of the algorithm shows that the execution time would at most exceed the optimal solution by a factor of around 1.6, in the worst-case. Simulations on randomly generated task graphs indicate that RDMS algorithm can reduce interconfiguration communication time by 11% and 44% respectively, compared with two other approaches that consider data dependency and hardware resource utilization only. The practicality, as well as efficiency of the proposed algorithm over other approaches, is demonstrated by simulating a task graph from a real-life application - N-body simulation - along with constraints for bandwidth and FPGA parameters from existing high-performance reconfigurable computers. Experiments on SRC-6 are carried out to validate the approach.

关键词： Algorithms Design Hardware task scheduling reconfigurable computing

来源：评论

学校读者我要写书评

暂无评论

UNILOGIC: A Novel Architecture for Highly Parallel reconfigurable systems

引用

acm transactions on reconfigurable technology and systems 2020年第4期13卷 21-21页

作者： Ioannou, Aggelos D. Georgopoulos, Konstantinos Malakonakis, Pavlos Pnevmatikatos, Dionisios N. Papaefstathiou, Vassilis D. Papaefstathiou, Ioannis Mavroidis, Iakovos Tech Univ Crete Sch ECE Iraklion 73100 Greece Telecommun Syst Inst Iraklion 73100 Greece Fdn Res & Technol Hellas FORTH N Plastira 100 Iraklion 70013 Greece Synelixis Solut Chalkida Greece Natl Tech Univ Athens Sch ECE Athens Greece Chalmers Univ Technol Comp Sci & Engn Gothenburg Sweden Aristotle Univ Thessaloniki Sch ECE Thessaloniki Greece

One of the main characteristics of High-performance Computing (HPC) applications is that they become increasingly performance and power demanding, pushing HPC systems to their limits. Existing HPC systems have not yet reached exascale performance mainly due to power limitations. Extrapolating from today's top HPC systems, about 100-200 MWatts would be required to sustain an exaflop-level of performance. A promising solution for tackling power limitations is the deployment of energy-efficient reconfigurable resources (in the form of Field-programmable Gate Arrays (FPGAs)) tightly integrated with conventional CPUs. However, current FPGA tools and programming environments are optimized for accelerating a single application or even task on a single FPGA device. In this work, we present UNILOGIC (Unified Logic), a novel HPC-tailored parallel architecture that efficiently incorporates FPGAs. UNILOGIC adopts the Partitioned Global Address Space (PGAS) model and extends it to include hardware accelerators, i.e., tasks implemented on the reconfigurable resources. The main advantages of UNILOGIC are that (i) the hardware accelerators can be accessed directly by any processor in the system, and (ii) the hardware accelerators can access any memory location in the system. In this way, the proposed architecture offers a unified environment where all the reconfigurable resources can be seamlessly used by any processor/operating system. The UNILOGIC architecture also provides hardware virtualization of the reconfigurable logic so that the hardware accelerators can be shared among multiple applications or tasks. The FPGA layer of the architecture is implemented by splitting its reconfigurable resources into (i) a static partition, which provides the PGAS-related communication infrastructure, and (ii) fixed-size and dynamically reconfigurable slots that can be programmed and accessed independently or combined together to support both line and coarse grain reconfiguration.(1) Finally,

关键词： Accelerators partial reconfiguration FPGA unification prototyping

来源：评论

学校读者我要写书评

暂无评论

The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator

引用

acm transactions on reconfigurable technology and systems 2015年第4期8卷 23-23页

作者： Thomas, David B. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

Gaussian random number generators (GRNGs) are an important component in parallel Monte Carlo simulations using FPGAs, where tens or hundreds of high-quality Gaussian samples must be generated per cycle using very few logic resources. This article describes the Table-Hadamard generator, which is a GRNG designed to generate multiple streams of random numbers in parallel. It uses discrete table distributions to generate pseudo-Gaussian base samples, then a parallel Hadamard transform to efficiently apply the central limit theorem. When generating 64 output samples, the Table-Hadamard requires just 130 slices per generated sample, which is a third of the resources needed by the next best technique, while still providing higher statistical quality.

关键词： Arithmetic operations parallel algorithms reconfigurable applications

来源：评论

学校读者我要写书评

暂无评论

A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically reconfigurable FPGA Partitioning

引用

acm transactions on reconfigurable technology and systems 2011年第2期4卷 16-16页

作者： Tai, Tzu-Chiang Lai, Yen-Tai Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

Dynamically reconfigurable FPGAs (DRFPGAs) have high logic utilization because of time-multiplexed interconnects and logic. In this article, we propose a performance-oriented algorithm for the DRFPGA partitioning problem. This algorithm partitions a given circuit system into stages such that the upper bound of the execution times of subcircuits is minimized. The communication cost is taken into consideration in the process of searching for the optimal solution. A graph is first constructed to represent the precedence constraints and calculate the number of buffers needed in a partitioning. This algorithm includes three phases. The first phase reduces the problem size by clustering the gates into subsystems that have only one output. Such a subsystem has a large number of intraconnections because the fan-outs of all vertices except for the one output are fed to the vertices inside the subsystem. This phase significantly reduces the computational complexity of partitioning. The second phase finds a partition with optimal performance. Finally, the third phase minimizes the communication cost by using an iterative improvement approach. Experimental results based on the Xilinx architecture show that our algorithm yields better partitioning solutions than traditional approaches.

关键词： Algorithms Design Performance Dynamically reconfigurable FPGA reconfigurable computing partitioning performance-oriented

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：