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Floating-Point Exponentiation Units for reconfigurable Computing

acm transactions on reconfigurable technology and systems 2013年第1期6卷 4-4页

作者： de Dinechin, Florent Echeverria, Pedro Lopez-Vallejo, Marisa Pasca, Bogdan Ecole Normale Super Lyon Lyon France Univ Politecn Madrid E-28040 Madrid Spain

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function x(y) as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

关键词： Design Algorithms Performance reconfigurable Computing floating-point power function exponentiation unit

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ReShape: Towards a High-Level Approach to Design and Operation of Modular reconfigurable systems

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acm transactions on reconfigurable technology and systems 2013年第1期6卷 5-5页

作者： Neely, Christopher E. Brebner, Gordon Shang, Weijia Xilinx Inc Xilinx Labs San Jose CA USA Santa Clara Univ Dept Comp Engn Santa Clara CA 95053 USA Santa Clara Univ Santa Clara CA 95053 USA

The latest FPGA devices provide the headroom to implement large-scale and complex systems. A key requirement is the integration of modules from diverse sources to promote modular design and reuse. A contrary factor is that using dynamic partial reconfiguration typically requires low-level planning of the system implementation. In this article, we introduce ReShape: a high-level approach for designing reconfigurable systems by interconnecting modules, which gives a "plug and play" look and feel, is supported by tools that carry out implementation functions, and is carried through to support system reconfiguration during operation. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules: for example, the streaming of data, or the reading and writing of data to and from memory modules. The details of wiring and signaling are hidden from view, via metadata associated with individual modules. This setting allows system reconfiguration at the module level, both by supporting type checking of replacement modules and by managing the overall system implementation, via metadata associated with its FPGA floorplan. The methodology and tools have been implemented in a prototype targeted to a domain-specific setting-high-speed networking-and have been validated on real telecommunications design projects.

关键词： Algorithms Design Languages Modular system design modular system reconfiguration high-level tools for FPGAs networking systems

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Self-reconfigurable Constant Multiplier for FPGA

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acm transactions on reconfigurable technology and systems 2013年第3期6卷 14-14页

作者： Hormigo, Javier Caffarena, Gabriel Oliver, Juan P. Boemo, Eduardo Univ Malaga Dept Comp Architecture E-29071 Malaga Spain Univ CEU San Pablo Dept Informat Technol Madrid Spain Univ Republica Fac Ingn Montevideo Uruguay Univ Autonoma Madrid E-28049 Madrid Spain

Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.

关键词： Design Algorithms Performance Constant multiplier runtime reconfiguration FPGA

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Virtualizable Hardware/Software Design Infrastructure for Dynamically Partially reconfigurable systems

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acm transactions on reconfigurable technology and systems 2013年第2期6卷 11-11页

作者： Huang, Chun-Hsian Hsiung, Pao-Ann Natl Taitung Univ Dept Comp Sci & Informat Engn Taitung Taiwan Natl Chung Cheng Univ Dept Comp Sci & Informat Engn Chiayi Taiwan

In most existing works, reconfigurable hardware modules are still managed as conventional hardware devices. Further, the software reconfiguration overhead incurred by loading corresponding device drivers into the kernel of an operating system has been overlooked until now. As a result, the enhancement of system performance and the utilization of reconfigurable hardware modules are still quite limited. This work proposes a virtualizable hardware/software design infrastructure (VDI) for dynamically partially reconfigurable systems. Besides the gate-level hardware virtualization provided by the partial reconfiguration technology, VDI supports the device-level hardware virtualization. In VDI, a reconfigurable hardware module can be virtualized such that it can be accessed efficiently by multiple applications in an interleaving way. A Hot-Plugin Connector (HPC) replaces the conventional device driver, such that it not only assists the device-level hardware virtualization but can also be reused across different hardware modules. To facilitate hardware/software communication and to enhance system scalability, the proposed VDI is realized as a hierarchical design framework. User-designed reconfigurable hardware modules can be easily integrated into VDI, and are then executed as hardware tasks in an operating system for reconfigurable systems (OS4RS). A dynamically partially reconfigurable network security system was designed using VDI, which demonstrated a higher utilization of reconfigurable hardware modules and a reduction by up to 12.83% of the processing time required by using the conventional method in a dynamically partially reconfigurable system.

关键词： Design Experimentation Dynamically partially reconfigurable systems hardware virtualization

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UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies

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acm transactions on reconfigurable technology and systems 2013年第3期6卷 13-13页

作者： Mehta, Gayatri Crawford, Carson Luo, Xiaozhong Parde, Natalie Patel, Krunalkumar Rodgers, Brandon Sistla, Anil Kumar Yadav, Anil Reisner, Marc Univ N Texas Denton TX 76203 USA Univ Nebraska Lincoln NE 68583 USA Johns Hopkins Univ Baltimore MD 21218 USA

The problem of creating efficient mappings of dataflow graphs onto specific architectures (i.e., solving the place and route problem) is incredibly challenging. The difficulty is especially acute in the area of Coarse-Grained reconfigurable Architectures (CGRAs) to the extent that solving the mapping problem may remove a significant bottleneck to adoption. We believe that the next generation of mapping algorithms will exhibit pattern recognition, the ability to learn from experience, and identification of creative solutions, all of which are human characteristics. This manuscript describes our game UNTANGLED, developed and fine-tuned over the course of a year to allow us to capture and analyze human mapping strategies. It also describes our results to date. We find that the mapping problem can be crowdsourced very effectively, that players can outperform existing algorithms, and that successful player strategies share many elements in common. Based on our observations and analysis, we make concrete recommendations for future research directions for mapping onto CGRAs.

关键词： Design Algorithms Performance reconfigurable architectures placement mapping algorithms game domain-specific custom architectures design automation

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Quipu: A Statistical Model for Predicting Hardware Resources

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acm transactions on reconfigurable technology and systems 2013年第1期6卷 3-3页

作者： Meeuws, Roel Ostadzadeh, S. Arash Galuzzi, Carlo Sima, Vlad Mihai Nane, Razvan Bertels, Koen Delft Univ Technol Dept Comp Sci & Engn NL-2600 AA Delft Netherlands

There has been a steady increase in the utilization of heterogeneous architectures to tackle the growing need for computing performance and low-power systems. The execution of computation-intensive functions on specialized hardware enables to achieve substantial speedups and power savings. However, with a large legacy code base and software engineering experts, it is not at all obvious how to easily utilize these new architectures. As a result, there is a need for comprehensive tool support to bridge the knowledge gap of many engineers as well as to retarget legacy code. In this article, we present the Quipu modeling approach, which consists of a set of tools and a modeling methodology that can generate hardware estimation models, which provide valuable information for developers. This information helps to focus their efforts, to partition their application, and to select the right heterogeneous components. We present Quipu's capability to generate domain-specific models, that are up to several times more accurate within their particular domain (error: 4.6%) as compared to domain-agnostic models (error: 23%). Finally, we show how Quipu can generate models for a new toolchain and platform within a few days.

关键词： Measurement Performance Design reconfigurable architectures modeling estimation statistics software complexity metrics system analysis and design

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An FPGA-Based Accelerator for Frequent Itemset Mining

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acm transactions on reconfigurable technology and systems 2013年第1期6卷 2-2页

作者： Zhang, Yan Zhang, Fan Jin, Zheming Bakos, Jason D. Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

In this article we describe a Field Programmable Gate Array (FPGA)-based coprocessor architecture for Frequent Itemset Mining (FIM). FIM is a common data mining task used to find frequently occurring subsets amongst a database of sets. FIM is a nonnumerical, data intensive computation and is used in machine learning and computational biology. FIM is particularly expensive-in terms of execution time and memory-when performed on large and/or sparse databases or when applied using a low appearance frequency threshold. Because of this, the development of increasingly efficient FIM algorithms and their mapping to parallel architectures is an active field. Previous attempts to accelerate FIM using FPGAs have relied on performance-limiting strategies such as iterative database loading and runtime logic unit reconfiguration. In this article, we present a novel architecture to implement Eclat, a well-known FIM algorithm. Unlike previous efforts, our technique does not impose limits on the maximum set size as a function of available FPGA logic resources and our design scales well to multiple FPGAs. In addition to a novel hardware design, we also present a corresponding compression scheme for intermediate results that are stored in on-chip memory. On a four-FPGA board, experimental results show up to 68X speedup compared to a highly optimized software implementation.

关键词： Performance Frequent itemset mining data mining Eclat data intensive co-processor high performance computing reconfigurable applications reconfigurable

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HC-CART: A Parallel System Implementation of Data Mining Classification and Regression Tree (CART) Algorithm on a Multi-FPGA System

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acm transactions ON ARCHITECTURE AND CODE OPTIMIZATION 2013年第4期9卷 47-47页

作者： Chrysos, Grigorios Dagritzikos, Panagiotis Papaefstathiou, Ioannis Dollas, Apostolos Tech Univ Crete Iraklion Greece

Data mining is a new field of computer science with a wide range of applications. Its goal is to extract knowledge from massive datasets in a human-understandable structure, for example, the decision trees. In this article we present an innovative, high-performance, system-level architecture for the Classification And Regression Tree (CART) algorithm, one of the most important and widely used algorithms in the data mining area. Our proposed architecture exploits parallelism at the decision variable level, and was fully implemented and evaluated on a modern high-performance reconfigurable platform, the Convey HC-1 server, that features four FPGAs and a multicore processor. Our FPGA-based implementation was integrated with the widely used "rpart" software library of the R project in order to provide the first fully functional reconfigurable system that can handle real-world large databases. The proposed system, named HC-CART system, achieves a performance speedup of up to two orders of magnitude compared to well-known single-threaded data mining software platforms, such as WEKA and the R platform. It also outperforms similar hardware systems which implement parts of the complete application by an order of magnitude. Finally, we show that the HC-CART system offers higher performance speedup than some other proposed parallel software implementations of decision tree construction algorithms.

关键词： Design Performance Algorithms Decision tree classification (DTC) classification and regression tree (CART) WEKA platform R project rpart library HW architecture reconfigurable system high-performance computing

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Architecture Customization of On-Chip reconfigurable Accelerators

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acm transactions ON DESIGN AUTOMATION OF ELECTRONIC systems 2013年第4期18卷 52-52页

作者： Yoon, Jonghee W. Lee, Jongeun Park, Sanghyun Kim, Yongjoo Lee, Jinyong Paek, Yunheung Cho, Doosan Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151600 South Korea ETRI Embedded SW Res Dept Next Generat OS Team Taejon 305350 South Korea UNIST Sch Elect & Comp Engn Ulsan 689798 South Korea Sunchon Natl Univ Sch Elect Engn Sunchon 540742 South Korea

Integrating coarse-grained reconfigurable architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without performing explicit design space exploration. In this article we present a novel methodology for incremental interconnect customization of CGRAs that can suggest a new interconnection architecture which is able to maximize the performance for a given set of application kernels while minimizing the hardware cost. In our methodology, we translate the problem of interconnect customization into that of inexact graph matching, and we devised a heuristic for A* search algorithm to efficiently solve the inexact graph matching problem. Our experimental results demonstrate that our customization method can quickly find application-optimized interconnections that exhibit 80% higher performance on average compared to the base architecture which has mesh interconnections, with little energy and hardware increase in interconnections and muxes.

关键词： Design Algorithms Performance Coarse-grained reconfigurable array interconnect architecture customization inexact matching graph edit customization

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Hardware Architectural Support for Control systems and Sensor Processing

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acm transactions ON EMBEDDED COMPUTING systems 2013年第2期13卷 16-16页

作者： Vyas, Sudhanshu Gupte, Adwait Gill, Christopher D. Cytron, Ron K. Zambreno, Joseph Jones, Phillip H. Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

The field of modern control theory and the systems used to implement these controls have shown rapid development over the last 50 years. It was often the case that those developing control algorithms could assume the computing medium was solely dedicated to the task of controlling a plant, for example, the control algorithm being implemented in software on a dedicated Digital Signal Processor (DSP), or implemented in hardware using a simple dedicated Programmable Logic Device (PLD). As time progressed, the drive to place more system functionality in a single component (reducing power, cost, and increasing reliability) has made this assumption less often true. Thus, it has been pointed out by some experts in the field of control theory (e. g., Astrom) that those developing control algorithms must take into account the effects of running their algorithms on systems that will be shared with other tasks. One aspect of the work presented in this article is a hardware architecture that allows control developers to maintain this simplifying assumption. We focus specifically on the Proportional-Integral-Derivative (PID) controller. An on-chip coprocessor has been implemented that can scale to support servicing hundreds of plants, while maintaining microsecond-level response times, tight deterministic control loop timing, and allowing the main processor to service noncontrol tasks. In order to control a plant, the controller needs information about the plant's state. Typically this information is obtained from sensors with which the plant has been instrumented. There are a number of common computations that may be performed on this sensor data before being presented to the controller (e. g., averaging and thresholding). Thus in addition to supporting PID algorithms, we have developed a Sensor Processing Unit (SPU) that off-loads these common sensor processing tasks from the main processor. We have prototyped our ideas using Field Programmable Gate Array (FPGA) technology. Th

关键词： Design Experimentation Measurement Control systems real-time systems sensor processing application-specific processor reconfigurable hardware

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