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Remote FPGA Lab for Enhancing Learning of Digital systems

acm transactions on reconfigurable technology and systems 2012年第3期5卷 1–13页

作者： Morgan, Fearghal Cawley, Seamus Newell, David Natl Univ Ireland Galway Ireland

Learning in digital systems can be enhanced through applying a learn-by-doing approach on practical hardware systems and by using Web-based technology to visualize and animate hardware behavior. The authors have reported the Web-based Remote FPGA Lab (RFL) which provides a novel, real-time control and visualization interface to a remote, always-on FPGA hardware implementation. The RFL helps students to understand and reason about digital systems operation, using interactive animation of signal behavior in an executing digital logic system, at any level of the design hierarchy. The RFL supports the creation of real-time interactive digital systems teaching demos. The article presents student RFL usage data and survey data which highlight improved student engagement, learning and achievement. The article describes the RFL architecture, communication interface, Web page functionality, user access administration and database management. The article also describes the RFLGen program, developed to automate user design integration into the Xilinx ISE VHDL-based RFL project wrapper for creation of FPGA configuration bitstreams and RFL animations.

关键词： Design Verification Remote FPGA laboratory digital systems education reconfigurable computing Web-based training

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Enhancing reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Enhancing Reconfigurable Platforms Programmability for Synch...

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6th International Workshop on reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Gantel, Laurent Khiar, Amel Miramond, Benoit Benkhelifa, Mohamed El Amine Kessal, Lounis Lemonnier, Fabrice Le Rhun, Jimmy Univ Cergy Pontoise ENSEA UMR CNRS 8051 ETISThales Res & Technol France Paris France

Recent FPGAs allow the design of efficient and complex Heterogeneous systems-on-Chip (HSoC). Namely, these systems are composed of several processors, hardware accelerators as well as communication media between all these components. Performances provided by HSoCs make them really interesting for data-flow applications, especially image processing applications. The use of this kind of architecture provides good performances but the drawback is an increase of the programming complexity. This complexity is due to the heterogeneous deployment of the application on the platform. Some functions are implemented in software to run on a processor, whereas other functions are implemented in hardware to run in a reconfigurable partition of the FPGA. This article aims to define a programming model based on the Synchronous Data-Flow model, in order to abstract the heterogeneity of the implementation and to leverage the communication issue between software and hardware actors.

关键词： Design Performance Languages reconfigurable computing data-flow programming real-time operating systems multiprocessor architectures FPGA image processing

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Memory Latency Hiding by Load Value Speculation for reconfigurable Computers

Memory Latency Hiding by Load Value Speculation for Reconfig...

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6th International Workshop on reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Thielmann, Benjamin Huthmann, Jens Koch, Andreas Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Tech Univ Darmstadt Darmstadt Germany

Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.

关键词： Design Performance FPGA high-level language compilation speculative execution memory interface

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Remote FPGA Lab for Enhancing Learning of Digital systems

Remote FPGA Lab for Enhancing Learning of Digital Systems

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6th International Workshop on reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Morgan, Fearghal Cawley, Seamus Newell, David Natl Univ Ireland Galway Ireland

关键词： Design Verification Remote FPGA laboratory digital systems education reconfigurable computing Web-based training

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reconfigurable Architecture for VBSME with Variable Pixel Precision

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acm transactions on reconfigurable technology and systems 2012年第1期5卷 3-3页

作者： Olivares, Joaquin Univ Cordoba Dept Comp Architecture Elect & Elect Technol Cordoba 14001 Spain

Current video coding standards, e.g. MPEG-4 H.264/AVC, include Variable Block Size Motion Estimation, in this paper, this process is implemented by a reconfigurable architecture based on Signed Digit arithmetic. Bit serial computation is applied to reconfigure pixel precision. The reconfigurable architectural model is extremely simple to reconfigure. Pixel truncation is used to speed up computation saving up 23.5% of clock cycles for 4-bit precision. This design allows to process all motion vectors of a block in just one iteration. This system has been implemented in FPGA, and HDTVp results are presented. Main characteristics, of this architecture are: very reduced cost, high performance, and reconfigurable pixel precision, these features could be useful in mobile devices.

关键词： Design Performance FPGA architectures video coding variable block size motion estimation MPEG reconfigurable devices signed digit bit serial computation pixel truncation

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On the Evolution of Hardware Circuits via reconfigurable Architectures

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acm transactions on reconfigurable technology and systems 2012年第4期5卷 22-22页

作者： Cancare, Fabio Bartolini, Davide B. Carminati, Matteo Sciuto, Donatella Santambrogio, Marco D. Politecn Milan Milan Italy MIT Cambridge MA 02139 USA

Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed-the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature. FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

关键词： Design Algorithms Performance Experimentation reconfigurable hardware dynamic partial reconfiguration evolvable hardware evolutionary circuit design

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SCF: A Framework for Task-Level Coordination in reconfigurable, Heterogeneous systems

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acm transactions on reconfigurable technology and systems 2012年第2期5卷 7-7页

作者： Aggarwal, Vikas Stitt, Greg George, Alan Yoon, Changil Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Gainesville FL 32611 USA

Heterogeneous computing systems comprised of accelerators such as FPGAs, GPUs, and manycore processors coupled with standard microprocessors are becoming an increasingly popular solution for future computing systems due to their higher performance and energy efficiency. Although programming languages and tools are evolving to simplify device-level design, programming such systems is still difficult and time-consuming largely due to system-wide challenges involving communication between heterogeneous devices, which currently require ad hoc solutions. Most communication frameworks and APIs which have dominated parallel application development for decades were developed for homogeneous systems, and hence cannot be directly employed for hybrid systems. To solve this problem, this article presents the System Coordination Framework (SCF), which employs message passing to transparently enable communication between tasks described using different programming tools (and languages), and running on heterogeneous processing devices of systems from domains ranging from embedded systems to High-Performance Computing (HPC) systems. By hiding low-level architectural details of the underlying communication from an application designer, SCF can improve application development productivity, provide higher levels of application portability, and offer rapid design-space exploration of different task/device mappings. In addition, SCF enables custom communication synthesis that exploits mechanisms specific to different devices and platforms, which can provide performance improvements over generic solutions employed previously. Our results indicate a performance improvement of 28x and 682x by employing FPGA devices for two applications presented in this article, while simultaneously improving the developer productivity by approximately 2.5 to 5 times by using SCF.

关键词： Design Languages Performance reconfigurable computing FPGA heterogeneous computing communication coordination productivity portability accelerators

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Dynamic Defragmentation of reconfigurable Devices

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acm transactions on reconfigurable technology and systems 2012年第2期5卷 8-8页

作者： Fekete, Sandor P. Kamphans, Tom Schweer, Nils Tessars, Christopher van der Veen, Jan C. Angermeier, Josef Koch, Dirk Teich, Juergen Braunschweig Univ Technol Dept Comp Sci Braunschweig Germany Univ Erlangen Nurnberg Dept Comp Sci 12 D-91054 Erlangen Germany

We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead;the objective is to maximize the length of contiguous free space that is available for new modules. We describe a number of algorithmic aspects of good defragmentation, and present an optimization method based on tabu search. Experimental results indicate that we can improve the quality of module layout by roughly 50% over the static layout. Among other benefits, this improvement avoids unnecessary rejections of modules.

关键词： Algorithms Defragmentation reconfigurable devices dynamic reconfiguration hardware/software codesign physical sorting complexity local search

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Low-Cost Sensing with Ring Oscillator Arrays for Healthier reconfigurable systems

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acm transactions on reconfigurable technology and systems 2012年第1期5卷 1-1页

作者： Zick, Kenneth M. Hayes, John P. Univ So Calif Inst Informat Sci Arlington VA 22217 USA Univ Michigan Dept Comp Sci & Engn Ann Arbor MI 48109 USA

Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip.

关键词： Design Measurement Performance Reliability Sensing FPGAs process variation voltage power leakage temperature wearout ring oscillator health management physically-adaptive computing

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reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing

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acm transactions on reconfigurable technology and systems 2012年第4期5卷 21-21页

作者： Jacobs, Adam Cieslewski, Grzegorz George, Alan D. Gordon-Ross, Ann Lam, Herman Univ Florida NSF Ctr High Performance Reconfigurable Comp CHRE Gainesville FL 32611 USA

Commercial SRAM-based, field-programmable gate arrays (FPGAs) have the potential to provide space applications with the necessary performance to meet next-generation mission requirements. However, mitigating an FPGA's susceptibility to single-event upset (SEU) radiation is challenging. Triple-modular redundancy (TMR) techniques are traditionally used to mitigate radiation effects, but TMR incurs substantial overheads such as increased area and power requirements. In order to reduce these overheads while still providing sufficient radiation mitigation, we propose a reconfigurable fault tolerance (RFT) framework that enables system designers to dynamically adjust a system's level of redundancy and fault mitigation based on the varying radiation incurred at different orbital positions. This framework includes an adaptive hardware architecture that leverages FPGA reconfigurable techniques to enable significant processing to be performed efficiently and reliably when environmental factors permit. To accurately estimate upset rates, we propose an upset rate modeling tool that captures time-varying radiation effects for arbitrary satellite orbits using a collection of existing, publically available tools and models. We perform fault-injection testing on a prototype RFT platform to validate the RFT architecture and RFT performability models. We combine our RFT hardware architecture and the modeled upset rates using phased-mission Markov modeling to estimate performability gains achievable using our framework for two case-study orbits.

关键词： Reliability Performance Design FPGA reconfigurable fault tolerance single-event upsets

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