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Internal Rehearsals for a reconfigurable Robot to Improve Area Coverage Performance

acm transactions ON INTELLIGENT systems AND technology 2024年第3期15卷 1-17页

作者： Samarakoon, S. M. Bhagya P. Muthugala, M. A. Viraj J. Elara, Mohan Rajesh Singapore Univ Technol & Design Engn Product Dev Pillar 8 Somapah Rd Singapore 487372 Singapore

reconfigurable robots are deployed for applications demanding area coverage, such as cleaning and inspections. Reconfiguration per context, considering beyond a small set of predefined shapes, is crucial for area coverage performance. However, the existing area coverage methods of reconfigurable robots are not always effective and require improvements for ascertaining the intended goal. Therefore, this article proposes a novel coverage strategy based on internal rehearsals to improve the area coverage performance of a reconfigurable robot. In this regard, a reconfigurable robot is embodied with the cognitive ability to predict the outcomes of its actions before executing them. A genetic algorithm uses the results of the internal rehearsals to determine a set of the robot's coverage parameters, including positioning, heading, and reconfiguration, to maximize coverage in an obstacle cluster encountered by the robot. The experimental results confirm that the proposed method can significantly improve the area coverage performance of a reconfigurable robot.

关键词： Internal rehearsals area coverage context-aware reconfiguration reconfigurable robots

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R-Blocks: An Energy-Efficient, Flexible, and Programmable CGRA

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acm transactions on reconfigurable technology and systems 2024年第2期17卷 1-34页

作者： De Bruin, Barry Vadivel, Kanishkan Wijtvliet, Mark Jaaskelainen, Pekka Corporaal, Henk Tampere Univ Tampere Pirkanmaa Finland Univ Technol Eindhoven Elect Syst Fac Elect Engn Eindhoven Noord Brabant Netherlands IMEC Eindhoven Netherlands ASMPT Ctr Competence Beuningen Netherlands

Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT) domain require complex on-device signal analysis and data reduction to maximize energy efficiency on these energy-constrained devices. Coarse-grained reconfigurable architectures (CGRAs) have been proposed as a good compromise between flexibility and energy efficiency for ultra-low power (ULP) signal processing. Existing CGRAs are often specialized and domain-specific or can only accelerate simple kernels, which makes accelerating complete applications on a CGRA while maintaining high energy efficiency an open issue. Moreover, the lack of instruction set architecture (ISA) standardization across CGRAs makes code generation using current compiler technology a major challenge. This work introduces R-Blocks;a ULP CGRA with HW/SW co-design tool-flow based on the OpenASIP toolset. This CGRA is extremely flexible due to its well-established VLIW-SIMD execution model and support for flexible SIMD-processing, while maintaining an extremely high energy efficiency using software bypassing, optimized instruction delivery, and local scratchpad memories. R-Blocks is synthesized in a commercial 22-nm FD-SOI technology and achieves a full-system energy efficiency of 115 MOPS/mW on a common FFT benchmark, 1.45x higher than a highly tuned embedded RISC-V processor. Comparable energy efficiency is obtained on multiple complex workloads, making R-Blocks a promising acceleration target for general-purpose computing.

关键词： Coarse-grained reconfigurable architecture HW/SW co-design code generation Energy efficiency

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Introduction to the IEEE transactions on Mobile Computing

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IEEE transactions on Mobile Computing 2002年第1期1卷 2-3页

作者： La, Porta, Thomas F. IEEE

No abstract available

关键词： Mobile Computing Pervasive Computing Computer Networks Application Software Computer Architecture Communication Networks IP Networks Web And Internet Services Communications technology Mobile Communication

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ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation

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acm transactions on reconfigurable technology and systems 2015年第1期9卷 1–17页

作者： Duarte, Rui Policarpo Bouganis, Christos-Savvas Univ London Imperial Coll Sci Technol & Med Elect & Elecctron Engn London SW7 2AZ England

Karhunen-Loeve Transformation is a widely used algorithm in signal processing that often implemented with high-throughput requisites. This work presents a novel methodology to optimise KLT designs on FPGAs that outperform typical design methodologies, through a prior characterisation of the arithmetic units in the datapath of the circuit under various operating conditions. Limited by the ever-increasing process variation, the delay models available in synthesis tools are no longer suitable for extreme performance optimisation of designs, and as they are generic, they need to consider the worst-case performance for a given fabrication process. Hence, they heavily penalise the maximum possible achieved performance of a design by leaving safety margin. This work presents a novel unified optimisation framework which contemplates a prior characterisation of the embedded multipliers on the target FPGA device under process, voltage, and temperature variation. The proposed framework allows a design space exploration leading to designs without any latency overheads that achieve high throughput while producing less errors than typical methodologies, operating with the same throughput. Experimental results demonstrate that the proposed methodology outperforms the typical implementation in three real-life design strategies: high performance, low power, and temperature variation;and it produced circuit designs that performed up to 18dB better when over-clocked.

关键词： Design Algorithms Performance Design methodologies digital signal processing reconfigurable applications optimisation over-clocking

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Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

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acm transactions ON DESIGN AUTOMATION OF ELECTRONIC systems 2018年第6期23卷 1–21页

作者： Winograd, Ted Shenoy, Gaurav Salmani, Hassan Mahmoodi, Hamid Rafatirad, Setareh Homayoun, Houman George Mason Univ 4400 Univ Dr Fairfax VA 22030 USA Howard Univ Washington DC 20059 USA San Francisco State Univ San Francisco CA 94132 USA

This article presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). An STT-based LUT with a significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance, and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT-based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study, conducted on a large number of standard circuit benchmarks, concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact on the performance of the circuit. We also tested these techniques against satisfiability attacks developed recently and show that these techniques also render more advanced reverse-engineering techniques computationally infeasible.

关键词： Reverse Engineering Hybrid CMOS-STT reconfigurable Gates Hardware Security Standard IC Design Flow

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Advantages of a Statistical Estimation Approach for Clock Frequency Estimation of Heterogeneous and Irregular CGRAs

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acm transactions on reconfigurable technology and systems 2023年第1期16卷 1-33页

作者： Wolf, Dennis Leander Spang, Christoph Diener, Daniel Hochberger, Christian Tech Univ Darmstadt Comp Syst Grp Merckstr 25 D-64283 Darmstadt Hessen Germany Tech Univ Darmstadt Embedded Syst & Applicat Grp Hochschulstr 10 D-64289 Darmstadt Hessen Germany

Estimating the maximum clock frequency of homogeneous Coarse Grained reconfigurable Arrays/Architectures (CGRAs) with an arbitrary number of Processing Elements (PE) is difficult. Clock frequency estimation of highly heterogeneous CGRAs takes additional factors into account, thus is even more difficult. Main challenges are the heterogeneous set of operators for each Processing Element (PE) and the irregular interconnect (connecting a CGRA's PEs). Multiple estimation approaches could be reasonable. We propose an optimized statistical estimator, which is based on our prior work. We demonstrate its superiority to state-of- the-art neural networks in terms of accuracy and robustness, especially in situations with a sparse set of training data.

关键词： Coarse grained reconfigurable architecture heterogeneity design space exploration automation machine learning

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NC-Library: Expanding SystemC Capabilities for Nested reconfigurable Hardware Modelling

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acm transactions on reconfigurable technology and systems 2024年第3期17卷 1-29页

作者： Haase, Julian Charaf, Najdet Gross, Alexander Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany Ctr Scalable Data Analyt & Artificial Intelligence Dresden Germany Tech Univ Dresden Ctr Tactile Internet Human In The Loop CeTI Dresden Germany

As runtime reconfiguration is used in an increasing number of hardware architectures, new simulation and modeling tools are needed to support the developer during the design phases. In this article, a language extension for SystemC is presented, together with a design methodology for the description and simulation of dynamically reconfigurable hardware at different levels of abstraction. The library presented offers a high degree of flexibility in the description of reconfiguration features and their management, while allowing runtime reconfiguration simulation, removal, and replacement of custom modules as well as third-party components throughout the architecture development process. In addition, our approach supports the emerging concept of nested reconfiguration and split regions with a minimal simulation overhead of a maximum of three delta cycles for signal and transaction forwarding, and four delta cycles for the reconfiguration process.

关键词： Simulation SystemC modeling dynamic partial reconfiguration nested reconfiguration

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Hardware-Software Codesign Based Accelerated and reconfigurable Methodology for String Matching in Computational Bioinformatics Applications

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IEEE-acm transactions ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 2020年第4期17卷 1198-1210页

作者： Gudur, Venkateshwarlu Y. Acharyya, Amit Indian Inst Technol Hyderabad Dept Elect Engn Hyderabad 502285 Telangana India

Research for new technologies and methods in computational bioinformatics has resulted in many folds biological data generation. To cope with the ever increasing growth of biological data, there is a need for accelerated solutions in various domains of computational bioinformatics. In these domains, string matching is a most versatile operation performed at various stages of the computational pipeline. For search patterns that are updated with time, there is a need for accelerated and reconfigurable string matching to perform faster searching in the ever-growing biological databases. In this paper, we have proposed an accelerated and real-time reconfigurable methodology for string matching using hardware-software codesign. Using state of the art field programmable gate arrays, we have proposed a complete system-on-chip solution for applications that require accelerated as well as real-time reconfigurable string matching. The proposed methodology is the first of its kind novel approach for high-speed string matching that also supports quick reconfiguration by patterns changing with time. It is verified at the string matching stage of protein identification. Experimental results show that the architectures designed using our proposed methodology are 4X faster than state-of-the-art software implementation running on a workstation and 1.5X-4X faster than hardware accelerators available in the literature.

关键词： Hardware acceleration hardware-software codesign real-time reconfiguration reconfigurable SoC FPGA string matching

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FDRA: A Framework for a Dynamically reconfigurable Accelerator Supporting Multi-Level Parallelism

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acm transactions on reconfigurable technology and systems 2024年第1期17卷 1-26页

作者： Qiu, Yunhui Mao, Yiqing Gao, Xuchen Chen, Sichao Li, Jiangnan Yin, Wenbo Wang, Lingli Fudan Univ State Key Lab ASIC & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China

Coarse-grained reconfigurable architectures (CGRAs) have emerged as promising accelerators due to their high flexibility and energy efficiency. However, existing open source works often lack integration of CGRAs with CPU systems and corresponding toolchains. Moreover, there is rare support for the accelerator instruction pipelining to overlap data communication, computation, and configuration across multiple tasks. In this article, we propose FDRA, an open source exploration framework for a heterogeneous system-on-chip (SoC) with a RISC-V processor and a dynamically reconfigurable accelerator (DRA) supporting loop, instruction, and task levels of parallelism. FDRA encompasses parameterized SoC modeling, Verilog generation, source-to-source application code transformation using frontend and DRA compilers, SoC simulation, and FPGA prototyping. FDRA incorporates the extraction of periodic accumulative operators and multi-dimensional linear load/store operators from nested loops. The DRA enables accessing the shared L2 cache with virtual addresses and supports direct memory access with arbitrary start addresses and data lengths. Integrated into the RISC-V Rocket SoC, our DRA achieves a remarkable 55x acceleration for loop kernels and improves energy efficiency by 29x. Compared to state-of-the-art RISC-V vector units, our DRA demonstrates a 2.9x speed improvement and 3.5x greater energy efficiency. In contrast to previous CGRA+RISC-V SoCs, our SoC achieves a minimum speedup of 5.2x.

关键词： CGRA dynamically reconfigurable accelerator instruction-level parallelism

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Particle Graphics on reconfigurable Hardware

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acm transactions on reconfigurable technology and systems 2008年第3期1卷 1-27页

作者： Beeckler, John S. Gross, Warren J. Department of Electrical and Computer Engineering McGill University 3480 University Street Montreal Quebec H3A 2A7 Canada

Particle graphics simulations are well suited for modeling complex phenomena such as water, cloth, explosions, fire, smoke, and clouds. They are normally realized in software as part of an interactive graphics application. The computational complexity of particle graphics simulations restricts the number of particles that can be updated in software at interactive frame rates. This article presents the design and implementation of a hardware particle graphics engine for accelerating real-time particle graphics simulations. We explore the design process, implementation issues, and limitations of using field-programmable gate arrays (FPGAs) for the acceleration of particle graphics. The FPGA particle engine processes million-particle systems at a rate from 47 to 112 million particles per second, which represents one to two orders of magnitude speedup over a 2.8 GHz CPU. Using three FPGAs, a maximum sustained performance of 112 million particles per second was achieved. © 2008, acm. All rights reserved.

关键词： Algorithms Design FPGAs particle systems Performance reconfigurable computing specialpurpose architectures

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