检索结果-内蒙古大学图书馆

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs

acm transactions on Design Automation of Electronic systems 2009年第4期14卷 1–26页

作者： Yuh, Ping-Hung Yang, Chia-Lin Li, Chi-Feng Lin, Chung-Hsiang Department of CISE National Taiwan University No. 1 Roosevelt Road Taipei Taiwan

As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabrics. In particular, we focus on eliminating leakage waste due to the delay between reconfiguration and execution time of a task. For partially dynamically reconfigurable FPGAs, the configuration prefetching technique is commonly used to hide runtime reconfiguration overhead. With prefetching, the configuration of a task is loaded into FPGAs as early as possible. Therefore, there is often a delay between reconfiguration and execution time of a task. In this period of time, the SRAM cells allocated to a task cannot be turned off even though they are not utilized. In this article, we propose a two-stage task scheduling methodology to reduce leakage waste due to the delay between reconfiguration and execution time of a task without sacrificing performance. In the first stage, a performance-driven task scheduler that targets at minimizing the schedule length is invoked to generate an initial placement. In the second stage, a postplacement leakage-aware task scheduling is applied to refine the initial placement such that leakage waste is minimized provided that the schedule length is not increased. To solve the postplacement leakage optimization problem, we propose two algorithms. The first one is an optimal algorithm based on Integer Linear Programming (ILP). The second algorithm is a heuristic approach that iteratively refines the placement to reduce leakage waste. Experimental results on real and synthetic designs show that the efficiency and effectiveness of the proposed postplacement leakage reduction techniques. © 2009 acm.

关键词： Integer programming

来源：评论

学校读者我要写书评

暂无评论

Memory Latency Hiding by Load Value Speculation for reconfigurable Computers

Memory Latency Hiding by Load Value Speculation for Reconfig...

引用

6th International Workshop on reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Thielmann, Benjamin Huthmann, Jens Koch, Andreas Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Tech Univ Darmstadt Darmstadt Germany

Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.

关键词： Design Performance FPGA high-level language compilation speculative execution memory interface

来源：评论

学校读者我要写书评

暂无评论

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

引用

acm transactions on reconfigurable technology and systems 2022年第2期15卷 1–33页

作者： Asiatici, Mikhail Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Sch Comp & Commun Sci EPFL IC IINFCOM LAP INF 137Batiment INFStn 14 CH-1015 Lausanne Switzerland

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24x area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

关键词： High performance computing reconfigurable computing nonblocking caches DRAM cuckoo hashing irregular memory accesses

来源：评论

学校读者我要写书评

暂无评论

A study of the applicability of existing exception-handling techniques to component-based real-time software technology

引用

acm transactions ON PROGRAMMING LANGUAGES AND systems 1998年第2期20卷 274-301页

作者： Lang, J Stewart, DB Univ Maryland Inst Adv Comp Studies Dept Elect Engn College Pk MD 20742 USA

This study focuses on the current state of error-handling technology and concludes with recommendations for further research in error handling for component-based real-time software. With real-time programs growing in size and complexity, the quality and cost of developing and maintaining them are still deep concerns to embedded software industries. Component-based software is a promising approach in reducing development cost while increasing quality and reliability. As with any other real-time software, component-based software needs exception detection and handling mechanisms to satisfy reliability requirements. The current lack of suitable error-handling techniques can make an application composed of reusable software nondeterministic and difficult to understand in the presence of errors.

关键词： component-based software error detection and handling faults reconfigurable software signals survey timing and deadline failures

来源：评论

学校读者我要写书评

暂无评论

Enhancing reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Enhancing Reconfigurable Platforms Programmability for Synch...

引用

6th International Workshop on reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Gantel, Laurent Khiar, Amel Miramond, Benoit Benkhelifa, Mohamed El Amine Kessal, Lounis Lemonnier, Fabrice Le Rhun, Jimmy Univ Cergy Pontoise ENSEA UMR CNRS 8051 ETISThales Res & Technol France Paris France

Recent FPGAs allow the design of efficient and complex Heterogeneous systems-on-Chip (HSoC). Namely, these systems are composed of several processors, hardware accelerators as well as communication media between all these components. Performances provided by HSoCs make them really interesting for data-flow applications, especially image processing applications. The use of this kind of architecture provides good performances but the drawback is an increase of the programming complexity. This complexity is due to the heterogeneous deployment of the application on the platform. Some functions are implemented in software to run on a processor, whereas other functions are implemented in hardware to run in a reconfigurable partition of the FPGA. This article aims to define a programming model based on the Synchronous Data-Flow model, in order to abstract the heterogeneity of the implementation and to leverage the communication issue between software and hardware actors.

关键词： Design Performance Languages reconfigurable computing data-flow programming real-time operating systems multiprocessor architectures FPGA image processing

来源：评论

学校读者我要写书评

暂无评论

Remote FPGA Lab for Enhancing Learning of Digital systems

Remote FPGA Lab for Enhancing Learning of Digital Systems

引用

6th International Workshop on reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Morgan, Fearghal Cawley, Seamus Newell, David Natl Univ Ireland Galway Ireland

Learning in digital systems can be enhanced through applying a learn-by-doing approach on practical hardware systems and by using Web-based technology to visualize and animate hardware behavior. The authors have reported the Web-based Remote FPGA Lab (RFL) which provides a novel, real-time control and visualization interface to a remote, always-on FPGA hardware implementation. The RFL helps students to understand and reason about digital systems operation, using interactive animation of signal behavior in an executing digital logic system, at any level of the design hierarchy. The RFL supports the creation of real-time interactive digital systems teaching demos. The article presents student RFL usage data and survey data which highlight improved student engagement, learning and achievement. The article describes the RFL architecture, communication interface, Web page functionality, user access administration and database management. The article also describes the RFLGen program, developed to automate user design integration into the Xilinx ISE VHDL-based RFL project wrapper for creation of FPGA configuration bitstreams and RFL animations.

关键词： Design Verification Remote FPGA laboratory digital systems education reconfigurable computing Web-based training

来源：评论

学校读者我要写书评

暂无评论

SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms

引用

acm transactions on reconfigurable technology and systems 2024年第3期17卷 1-28页

作者： Lu, Alec Narendra, Jahanvi Fang, Zhenman Simon Fraser Univ Sch Engn Sci Burnaby BC Canada Simon Fraser Univ Burnaby BC Canada

Today's big data query engines are constantly under pressure to keep up with the rapidly increasing demand for faster processing of more complex workloads. In the past few years, FPGA-based database acceleration efforts have demonstrated promising performance improvement with good energy efficiency. However, few studies target the programming and design automation support to leverage the FPGA accelerator benefits in query processing. Most of them rely on the SQL query plan generated by CPU query engines and manually map the query plan onto the FPGA accelerators, which is tedious and error-prone. Moreover, such CPU-oriented query plans do not consider the utilization of FPGA accelerators and could lose more optimization opportunities. In this article, we present SQL2FPGA, an FPGA accelerator-aware compiler to automatically map SQL queries onto the heterogeneous CPU-FPGA platforms. Our SQL2FPGA front-end takes an optimized logical plan of an SQL query from a database query engine and transforms it into a unified operator-level intermediate representation. To generate an optimized FPGA-aware physical plan, SQL2FPGA implements a set of compiler optimization passes to (1) improve operator acceleration coverage by the FPGA, (2) eliminate redundant computation during physical execution, and (3) minimize data transfer overhead between operators on the CPU and FPGA. Furthermore, it also leverages machine learning techniques to predict and identify the optimal platform, either CPU or FPGA, for the physical execution of individual query operations. Finally, SQL2FPGA generates the associated query acceleration code for heterogeneous CPU-FPGA system deployment. Compared to the widely used Apache Spark SQL framework running on the CPU, SQL2FPGA-using two AMD/Xilinx HBM-based Alveo U280 FPGA boards and Ver.2020 AMD/Xilinx FPGA overlay designs-achieves an average performance speedup of 10.1x and 13.9x across all 22 TPC-H benchmark queries in a scale factor of 1 GB (SF1) and 30 GB (

关键词： Hardware- Hardware accelerators Hardware-software codesign Computer systems organization- reconfigurable computing High-level language architectures

来源：评论

学校读者我要写书评

暂无评论

MORPHEUS: A Heterogeneous Dynamically reconfigurable Platform for Designing Highly Complex Embedded systems

引用

acm transactions ON EMBEDDED COMPUTING systems 2013年第3期12卷 1-33页

作者： Voros, Nikolaos S. Hubner, Michael Becker, Juergen Kuhnle, Matthias Thomaitiv, Florian Grasset, Arnaud Brelet, Paul Bonnot, Philippe Campi, Fabio Schuler, Eberhard Sahlbach, Henning Whitty, Sean Ernst, Rolf Billich, Enrico Tischendorf, Claudia Heinkel, Ulrich Ieromnimon, Frank Kritharidis, Dimitrios Schneider, Axel Knaeblein, Joachim Putzke-Roming, Wolfram Univ Karlsruhe TII Karlsruhe Germany Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Alcatel Lucent Murray Hill NJ USA

Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that respect, this paper introduces an innovative technology platform, called MORPHEUS, which intents to provide complete design framework for dealing with the aforementioned challenges. MORPHEUS consists of a state of the art architecture that encompasses heterogeneous reconfigurable accelerators for implementing on the same hardware architecture applications with varying characteristics and a tool chain that, through a software oriented approach, eases the implementation of highly complex applications with heterogeneous characteristics. The proposed approach has been tested and evaluated through state of the art cases studies borrowed from complementary application domains.

关键词： Algorithms Design Experimentation Performance Verification

来源：评论

学校读者我要写书评

暂无评论

Data and Computation Reuse in CNNs Using Memristor TCAMs

引用

acm transactions on reconfigurable technology and systems 2023年第1期16卷 1-24页

作者： de Moura, Rafael Fao Cardoso de Lima, Joao Paulo Carro, Luigi Univ Fed Rio Grande do Sul Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

Exploiting computational and data reuse in CNNs is crucial for the successful design of resource-constrained platforms. In image recognition applications, high levels of input locality and redundancy present in CNNs have become the golden goose for skipping costly arithmetic operations. One promising technique for this consists in storing function responses of some input patterns into offline lookup tables and replacing online computation with search operations, which are highly efficient when implemented by emerging non-volatile memory technologies. In this work, we rethink both algorithm and architecture for exploiting locality and reuse opportunities by replacing entire convolutions with searches on Content-addressable Memories. By previously calculating convolution results and building compact lookup tables with our novel clustering algorithm, one can evaluate activations at constant time complexity, also requiring a single read operation of the current input tensor. Then, we devise a reconfigurable array of processing elements based on memristive Ternary Content-addressable Memories to efficiently implement the algorithmic solution and meet the flexibility requirements of several CNN architectures. Results show that our design reduces the number of multiplications and memory accesses proportionally to the number of convolutional layer channels. The average performance is 1,172 and 82 FPS for AlexNet and VGG-16 models, thus outperforming state-of-the-art works by 13x.

关键词： Neural network accelerators Ternary Content-addressable Memories (TCAM) in-memory processing reconfigurable computing

来源：评论

学校读者我要写书评

暂无评论

A Hardware Design Framework for Computer Vision Models Based on reconfigurable Devices

引用

acm transactions on reconfigurable technology and systems 2024年第1期17卷 1-31页

作者： Fan, Zimeng Hu, Wei Liu, Fang Xu, Dian Guo, Hong He, Yanxiang Peng, Min Wuhan Univ Sci & Technol 10 West Huangjiahu RdQingling St Wuhan Hubei Peoples R China Wuhan Univ 299 Bayi Rd Wuhan Hubei Peoples R China Wuhan Inst City 299 Bayi Rd Wuhan Hubei Peoples R China Wuhan Univ Sch Comp Sci 299 Bayi Rd Wuhan Hubei Peoples R China

In computer vision, the joint development of the algorithm and computing dimensions cannot be separated. Models and algorithms are constantly evolving, while hardware designs must adapt to new or updated algorithms. reconfigurable devices are recognized as important platforms for computer vision applications because of their reconfigurability. There are two typical design approaches: customized and overlay design. However, existing work is unable to achieve both efficient performance and scalability to adapt to a wide range of models. To address both considerations, we propose a design framework based on reconfigurable devices to provide unified support for computer vision models. It provides software-programmable modules while leaving unit design space for problem-specific algorithms. Based on the proposed framework, we design a model mapping method and a hardware architecture with two processor arrays to enable dynamic and static reconfiguration, thereby relieving redesign pressure. In addition, resource consumption and efficiency can be balanced by adjusting the hyperparameter. In experiments on CNN, vision Transformer, and vision MLP models, our work's throughput is improved by 18.8x-33.6x and 1.4x-2.0x compared to CPU and GPU. Compared to others on the same platform, accelerators based on our framework can better balance resource consumption and efficiency.

关键词： FPGA hardware acceleration hardware

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：