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Note from the TRETS EiC about the new Journal-first track in FPT'21

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acm transactions on reconfigurable technology and systems 2022年第1期15卷 1页

作者： Chen, Deming ACM Transact Reconfigurable Technol & Syst TRETS New York NY 10121 USA

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Design of Distributed reconfigurable Robotics systems with ReconROS

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acm transactions on reconfigurable technology and systems 2022年第3期15卷 27-27页

作者： Lienen, Christian Platzner, Marco Paderborn Univ Dept Comp Sci Comp Engn Grp Warburger Str 100 D-33098 Paderborn Germany

Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.

关键词： Robot operating sysstem (ROS) FPGA acceleration robotics

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AHA: An Agile Approach to the Design of Coarse-Grained reconfigurable Accelerators and Compilers

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acm transactions ON EMBEDDED COMPUTING systems 2023年第2期22卷 35-35页

作者： Koul, Kalhan Melchert, Jackson Sreedhar, Kavya Truong, Leonard Nyengele, Gedeon Zhang, Keyi Liu, Qiaoyi Setter, Jeff Chen, Po-Han Mei, Yuchen Strange, Maxwell Daly, Ross Donovick, Caleb Carsello, Alex Kong, Taeyoung Feng, Kathleen Huff, Dillon Nayak, Ankita Setaluri, Rajsekhar Thomas, James Bhagdikar, Nikhil Durst, David Myers, Zachary Tsiskaridze, Nestan Richardson, Stephen Bahr, Rick Fatahalian, Kayvon Hanrahan, Pat Barrett, Clark Horowitz, Mark Torng, Christopher Kjolstad, Fredrik Raina, Priyanka Stanford Univ 450 Serra Mall Stanford CA 94305 USA

With the slowing of Moore's law, computer architects have turned to domain-specific hardware specialization to continue improving the performance and efficiency of computing systems. However, specialization typically entails significant modifications to the software stack to properly leverage the updated hardware. The lack of a structured approach for updating the compiler and the accelerator in tandem has impeded many attempts to systematize this procedure. We propose a new approach to enable flexible and evolvable domain-specific hardware specialization based on coarse-grained reconfigurable arrays (CGRAs). Our agile methodology employs a combination of new programming languages and formal methods to automatically generate the accelerator hardware and its compiler from a single source of truth. This enables the creation of design-space exploration frameworks that automatically generate accelerator architectures that approach the efficiencies of hand-designed accelerators, with a significantly lower design effort for both hardware and compiler generation. Our current system accelerates dense linear algebra applications but is modular and can be extended to support other domains. Our methodology has the potential to significantly improve the productivity of hardware-software engineering teams and enable quicker customization and deployment of complex accelerator-rich computing systems.

关键词： Hardware accelerators coarse-grained reconfigurable arrays domainspecific languages image processing

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Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically reconfigurable systems

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acm transactions ON DESIGN AUTOMATION OF ELECTRONIC systems 2023年第1期28卷 7-7页

作者： Ding, Bo Huang, Jinglei Xu, Qi Wang, Junpeng Chen, Song Kang, Yi Univ Sci & Technol China Sch Microelect Hefei Peoples R China Univ Sci & Technol China Dept Elect Sci & Technol Hefei Peoples R China Univ Sci & Technol China Hefei Comprehens Natl Sci Ctr Sch Microelect Inst Artifcial Intelligence Hefei Peoples R China

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floor-planning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

关键词： Memory allocation memory block allocation on-chip/off-chip memory block assignment partially dynamically reconfigurabe systems

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FPGA HLS Today: Successes, Challenges, and Opportunities

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acm transactions on reconfigurable technology and systems 2022年第4期15卷 51-51页

作者： Cong, Jason Lau, Jason Liu, Gai Neuendorffer, Stephen Pan, Peichen Vissers, Kees Zhang, Zhiru Univ Calif Los Angeles 468A Engn 6 Los Angeles CA 90095 USA Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Falcon Comp Solut Inc 1580 Summerfield Dr Campbell CA 95008 USA Cornell Univ 320 Rhodes Hall Ithaca NY 14853 USA

The year 2011 marked an important transition for FPGA high-level synthesis (HLS), as it went from prototyping to deployment. A decade later, in this article, we assess the progress of the deployment of HLS technology and highlight the successes in several application domains, including deep learning, video transcoding, graph processing, and genome sequencing. We also discuss the challenges faced by today's HIS technology and the opportunities for further research and development, especially in the areas of achieving high clock frequency, coping with complex pragmas and system integration, legacy code transformation, building on open source HIS infrastructures, supporting domain-specific languages, and standardization. It is our hope that this article will inspire more research on FPGA HIS and bring it to a new height.

关键词： High-level synthesis design automation design tools electronic design automation FPGA architecture FPGA acceleration customizable computing hardware compiler hardware description reconfigurable applications

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Hardware-Software Codesign Based Accelerated and reconfigurable Methodology for String Matching in Computational Bioinformatics Applications

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IEEE-acm transactions ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 2020年第4期17卷 1198-1210页

作者： Gudur, Venkateshwarlu Y. Acharyya, Amit Indian Inst Technol Hyderabad Dept Elect Engn Hyderabad 502285 Telangana India

Research for new technologies and methods in computational bioinformatics has resulted in many folds biological data generation. To cope with the ever increasing growth of biological data, there is a need for accelerated solutions in various domains of computational bioinformatics. In these domains, string matching is a most versatile operation performed at various stages of the computational pipeline. For search patterns that are updated with time, there is a need for accelerated and reconfigurable string matching to perform faster searching in the ever-growing biological databases. In this paper, we have proposed an accelerated and real-time reconfigurable methodology for string matching using hardware-software codesign. Using state of the art field programmable gate arrays, we have proposed a complete system-on-chip solution for applications that require accelerated as well as real-time reconfigurable string matching. The proposed methodology is the first of its kind novel approach for high-speed string matching that also supports quick reconfiguration by patterns changing with time. It is verified at the string matching stage of protein identification. Experimental results show that the architectures designed using our proposed methodology are 4X faster than state-of-the-art software implementation running on a workstation and 1.5X-4X faster than hardware accelerators available in the literature.

关键词： Hardware acceleration hardware-software codesign real-time reconfiguration reconfigurable SoC FPGA string matching

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Partitioning and Scheduling with Module Merging on Dynamic Partial reconfigurable FPGAs

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acm transactions on reconfigurable technology and systems 2020年第3期13卷 16-16页

作者： Tang, Qi Wang, Zhe Guo, Biao Zhu, Li-Hua Wei, Ji-Bo Natl Univ Def Technol 109 Deya Rd Changsha 410073 Hunan Peoples R China Hunan Univ 2 South Lushan Rd Changsha 410082 Hunan Peoples R China

Field programmable gate array (FPGA) is ubiquitous nowadays and is applied to many areas. Dynamic partial reconfiguration (DPR) is introduced to most modern FPGAs, enabling changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. However, delivering the powerful capacity of the DPR FPGA to the user depends on the efficient partitioning and scheduling technology. This article proposes the module merging technique for the partitioning and scheduling problem to reduce the reconfiguration overhead and improve the schedule performance. An exact approach based on the integer linear programming (ILP) for the partitioning and scheduling problem with module merging is proposed. The ILP-based approach is capable of solving the problem optimally, and can be used to further improve the performance of schedules produced by other non-optimal algorithms;however, it is time-consuming to solve large-scale problems. Therefore, a K-sliced-ILP algorithm based on the methodology of divide-arid-conquer is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. Experiments are carried out with a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.

关键词： Dynamic partial reconfiguration partitioning scheduling integer linear programming

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Accelerating Weather Prediction Using Near-Memory reconfigurable Fabric

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acm transactions on reconfigurable technology and systems 2022年第4期15卷 39-39页

作者： Singh, Gagandeep Diamantopoulos, Dionysios Gomez-Luna, Juan Hagleitner, Christoph Stuijk, Sander Corporaal, Henk Mutlu, Onur IBM Res Europe Zurich Lab Zurich Switzerland Eindhoven Univ Technol Eindhoven Netherlands

Ongoing climate change calls for fast and accurate weather and climate modeling. However, when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU implementations suffer from limited performance and high energy consumption. These implementations are dominated by complex irregular memory access patterns and low arithmetic intensity that pose fundamental challenges to acceleration. To overcome these challenges, we propose and evaluate the use of near-memory acceleration using a reconfigurable fabric with high-bandwidth memory (HBM). We focus on compound stencils that are fundamental kernels in weather prediction models. By using high-level synthesis techniques, we develop NERO, an field-programmable gate array+HBM-based accelerator connected through Open Coherent Accelerator Processor Interface to an IBM POWER9 host system. Our experimental results show that NERO outperforms a 16-core POWER9 system by 5.3x and 12.7x when running two different compound stencil kernels. NERO reduces the energy consumption by 12x and 35x for the same two kernels over the POWER9 system with an energy efficiency of 1.61 GFLOPS/W and 21.01 GFLOPS/W. We conclude that employing near-memory acceleration solutions for weather prediction modeling is promising as a means to achieve both high performance and high energy efficiency.

关键词： FPGA near-memory computing weather modeling high-performance computing processing in memory

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ROC: A reconfigurable Optical Computer for Simulating Physical Processes

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acm transactions ON PARALLEL COMPUTING 2020年第1期7卷 1–29页

作者： Anderson, Jeff Kayraklioglu, Engin Sun, Shuai Crandall, Joseph Alkabani, Yousra Narayana, Vikram Sorger, Volker El-Ghazawi, Tarek George Washington Univ 800 22nd St NW5000 Sci & Engn Hall Washington DC 20052 USA Halmstad Univ Halmstad Sweden Intel Corp Santa Clara CA 95051 USA

Due to the end of Moore's law and Dennard scaling, we are entering a new era of processors. Computing systems are increasingly facing power and performance challenges due to both device- and circuit-related challenges with resistive and capacitive charging. Non-von Neumann architectures are needed to support future computations through innovative post-Moore's law architectures. To enable these emerging architectures with high-performance and at ultra-low power, both parallel computation and inter-node communication on-the-chip can be supported using photons. To this end, we introduce ROC, a reconfigurable optical computer that can solve partial differential equations (PDEs). PDE solvers form the basis for many traditional simulation problems in science and engineering that are currently performed on supercomputers. Instead of solving problems iteratively, the proposed engine uses a resistive mesh architecture to solve a PDE in a single iteration (one-shot). Instead of using actual electrical circuits, the physical underlying hardware emulates such structures using a silicon-photonics mesh that splits light into separate pathways, allowing it to add or subtract optical power analogous to programmable resistors. The time to obtain the PDE solution then only depends on the time-of-flight of a photon through the programmed mesh, which can be on the order of 10's of picoseconds given the millimeter-compact integrated photonic circuit. Numerically validated experimental results show that, over multiple configurations, ROC can achieve several orders of magnitude improvement over state-of-the-art GPUs when speed, power, and size are taken into account. Further, it comes within approximately 90% precision of current numerical solvers. As such, ROC can be a viable reconfigurable, approximate computer with the potential for more precise results when replacing silicon-photonics building blocks with nanoscale photonic lumped-elements.

关键词： PDE solver accelerator approximate computing nanophotonic computing analog computing optical computing post-Moore's law processors

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Analytical Performance Estimation for Large-Scale reconfigurable Dataflow Platforms

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acm transactions on reconfigurable technology and systems 2021年第3期14卷 12-12页

作者： Yasudo, Ryota Coutinho, Jose G. F. Varbanescu, Ana-Lucia Luk, Wayne Amano, Hideharu Becker, Tobias Guo, Ce Hiroshima Univ 1-4-1 Kagamiyama Higashihiroshima Hiroshima 7398527 Japan Imperial Coll London 180 Queens Gate London SW7 2BZ England Univ Amsterdam Postbus 94323 NL-1090 GH Amsterdam Netherlands Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa 2238522 Japan Maxeler Technol Ltd 3 Hammersmith Grove London W6 0ND England

Next-generation high-performance computing platforms will handle extreme data- and compute-intensive problems that are intractable with today's technology. A promising path in achieving the next leap in high-performance computing is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators such as FPGAs, which have been shown to speed up compute-intensive tasks with reduced power consumption. However, assessing the feasibility of large-scale heterogeneous systems requires fast and accurate performance prediction. This article proposes Performance Estimation for reconfigurable Kernels and systems (PERKS), a novel performance estimation framework for reconfigurable dataflow platforms. PERKS makes use of an analytical model with machine and application parameters for predicting the performance of multi-accelerator systems and detecting their bottlenecks. Model calibration is automatic, making the model flexible and usable for different machine configurations and applications, including hypothetical ones. Our experimental results show that PERKS can predict the performance of current workloads on reconfigurable dataflow platforms with an accuracy above 91%. The results also illustrate how the modelling scales to large workloads, and how performance impact of architectural features can be estimated in seconds.

关键词： Performance modelling heterogeneous systems reconfigurable dataflow platforms FPGAs

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