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作者： Agne, Andreas Happe, Markus Lösch, Achim Plessl, Christian Platzner, Marco Department of Computer Science University of Paderborn Germany

Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems. © 2014 acm.

关键词： reconfigurable architectures

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Scheduling and placement of hardware/software real-time relocatable tasks in dynamically partially reconfigurable systems

Scheduling and placement of hardware/software real-time relo...

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作者： Hsiung, Pao-Ann Huang, Chun-Hsian Shen, Jih-Sheng Chiang, Chen-Chi National Chung Cheng University 168 University Road Min-Hsiung Chiayi 62102 Taiwan

With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime task relocation. In this work, we propose a new Relocatable Hardware-Software Scheduling (RHSS) method that not only can be applied to dynamically relocatable hardware-software tasks, but also increases the reconfigurable hardware resource utilization, reduces the reconfigurable hardware resource fragmentation with realistic placement methods, and makes best efforts at meeting the real-time constraints of tasks. The feasibility of the proposed relocatable hardware-software scheduling algorithm was proved by applying it to some randomly generated examples and a real dynamically reconfigurable network security system example. Compared to the quadratic time complexity of the state-of-the-art Adaptive Hardware-Software Allocation (AHSA) method, RHSS is linear in time complexity, and improves the reconfigurable hardware utilization by as much as 117.8%. The scheduling and placement time and the memory usage are also drastically reduced by as much as 89.5% and 96.4%, respectively. © 2010 acm.

关键词： reconfigurable hardware

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reconfigurable Framework for Resilient Semantic Segmentation for Space Applications

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acm transactions on reconfigurable technology and systems 2021年第4期14卷 1-32页

作者： Sabogal, Sebastian George, Alan Crum, Gary Univ Pittsburgh NSF SHREC Ctr Swanson Sch Engn Pittsburgh PA 15213 USA NASA Goddard Space Flight Ctr Sci Data Proc Branch Code 587 Greenbelt MD 20771 USA

Deep learning (DL) presents new opportunities for enabling spacecraft autonomy, onboard analysis, and intelligent applications for space missions. However, DL applications are computationally intensive and often infeasible to deploy on radiation-hardened (rad-hard) processors, which traditionally harness a fraction of the computational capability of their commercial-off-the-shelf counterparts. Commercial FPGAs and systemon-chips present numerous architectural advantages and provide the computation capabilities to enable onboard DL applications;however, these devices are highly susceptible to radiation-induced single-event effects (SEEs) that can degrade the dependability of DL applications. In this article, we propose reconfigurable ConvNet (RECON), a reconfigurable acceleration framework for dependable, high-performance semantic segmentation for space applications. In RECON, we propose both selective and adaptive approaches to enable efficient SEE mitigation. In our selective approach, control-flow parts are selectively protected by triple-modular redundancy to minimize SEE-induced hangs, and in our adaptive approach, partial reconfiguration is used to adapt the mitigation of dataflow parts in response to a dynamic radiation environment. Combined, both approaches enable RECON tomaximize system performability subject to mission availability constraints. We perform fault injection and neutron irradiation to observe the susceptibility of RECON and use dependability modeling to evaluate RECON in various orbital case studies to demonstrate a 1.5-3.0x performability improvement in both performance and energy efficiency compared to static approaches.

关键词： Environmentally adaptive computing dependability modeling space computing single-event effects

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Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains

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acm transactions on reconfigurable technology and systems 2023年第2期16卷 1-28页

作者： Nayak, Ankita Zhang, Keyi Setaluri, Rajsekhar Carsello, Alex Mann, Makai Torng, Christopher Richardson, Stephen Bahr, Rick Hanrahan, Pat Horowitz, Mark Raina, Priyanka Stanford Univ Stanford CA 94305 USA

To effectively minimize static power for a wide range of applications, power domains for coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained than those found in a typical applicationspecific integrated circuit. However, the special isolation logic needed to ensure electrical protection between off and on domains makes fine-grained power domains area- and timing-inefficient. We propose a novel design of the CGRA routing fabric that reduces the area overhead of power domain boundary protection from around 9% to less than 1% without incurring any extra timing delay from the isolation cells. Conventional Unified Power Format based flow for power domain boundary protection does not support this design choice. Therefore, we create our own compiler-like passes that iteratively introduce the needed design changes, and formally verify the transformations using methods based on satisfiability modulo theories. These passes also let us optimize how we handle test and debug signals through the off tiles in the CGRA. Using our framework, we add power domains to a CGRA that we designed and taped out. The CGRA has 32x16 processing element and memory tiles and 4-MB secondary memory. We address the implementation challenges encountered due to the introduction of fine-grained power domains, including the addressing of the CGRA tiles, the power grid design, well substrate connections, and distribution of global signals. Our CGRA achieves up to 83% reduction in leakage power and 26% reduction in total power versus an identical CGRA without multiple power domains, for a range of image processing and machine learning applications.

关键词： reconfigurable computing coarse-grained reconfigurable arrays power domains hardware generators

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PVoT: reconfigurable Photovoltaic Array for Indoor Light Energy-Powered Batteryless Devices

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2022年第11期41卷 4181-4192页

作者： Kim, Jiwon Kim, Eunyeong Jeon, Seunghyeok Ahn, Junick Jun, Hyungchol Cha, Hojung Yonsei Univ Dept Comp Sci Seoul 03722 South Korea

Multiple photovoltaic (PV) modules are often used to provide enhanced harvesting capability for light energy-based Internet of Things (IoT) devices. PV modules facing multiple directions can lead to a situational energy loss when parts of the modules are shaded. To address this issue, existing solutions exploit reconfigurable PV arrays to acquire the optimal configuration in a given situation. However, conventional techniques are not energy efficient in estimating the harvesting capability of PV modules, and require high computation to find the optimal PV array at runtime. In this article, we propose PVoT, an energy-efficient reconfigurable PV array, which maximizes the harvesting energy for indoor IoT devices. To this end, we propose the use of photoresistors to estimate the harvesting capability with minimal energy overhead. We also provide hardware and software schemes, which perform event-driven light change detection in an energy-efficient way. Furthermore, we develop a power imbalance threshold metric to quickly find the optimal PV array at runtime. We implemented a prototype PVoT with off-the-shelf components and accompanying software. Experiments with the prototype hardware showed that PVoT achieves a gain of up to 23.9% in harvested energy compared to the existing directly connected PV array scheme.

关键词： Energy harvesting low-power system photovoltaic (PV) systems reconfigurable architectures shading effect

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A Desktop Computer with a reconfigurable Pentium

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acm transactions on reconfigurable technology and systems 2008年第1期1卷 1-15页

作者： Shih-Lien, L. Lu Yiannacouras, Peter Suh, Taeweon Kassa, Rolf Konow, Michael Intel Corporation Hillsboro Mailstop: JF2-04 2111 NE 25th Avenue OR 97229 United States Department of Electrical and Computer Engineering University of Toronto Toronto 10 King's College Road Ont. Canada M5S 3G4 Canada Intel Corporation Hillsboro Mailstop: JF5-254 2111 NE 25th Avenue OR 97229 Georgia Intel Corporation Braunschweig Theodor-Heuss-Str. 7 38122 Germany

Advancements in reconfigurable technologies, specifically FPGAs, have yielded faster, more powerefficient reconfigurable devices with enormous capacities. In our work, we provide testament to the impressive capacity of recent FPGAs by hosting a complete Pentium R in a single FPGA chip. In addition we demonstrate how FPGAs can be used for microprocessor design space exploration while overcoming the tension between simulation speed, model accuracy, and model completeness found in traditional software simulator environments. Specifically, we perform preliminary experimentation/prototyping with an original Socket 7 based desktop processor system with typical hardware peripherals running modern operating systems such as Fedora Core 4 and Windows XP;however we have inserted a Xilinx Virtex-4 in place of the processor that should sit in the motherboard and have used the Virtex-4 to host a complete version of the Pentium R microprocessor (which consumes less than half its resources). We can therefore apply architectural changes to the processor and evaluate their effects on the complete desktop system. We use this FPGA-based emulation system to conduct preliminary architectural experiments including growing the branch target buffer and the level 1 caches. In addition, we experimented with interfacing hardware accelerators such as DES and AES engines which resulted in a 27x speedup. © 2008, acm. All rights reserved.

关键词： accelerator architecture Design emulator exploration FPGA Measurement model operating system Pentium R Performance processor reconfigurable simulator

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Using Memory Profile Analysis for Automatic Synthesis of Pointers Code

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acm transactions ON EMBEDDED COMPUTING systems 2013年第3期12卷 1-21页

作者： Ben-Asher, Yosi Rotem, Nadav Univ Haifa IL-31999 Haifa Israel

One of the main advantages of high-level synthesis (HLS) is the ability to synthesize circuits that can access multiple memory banks in parallel. Current HLS systems synthesize parallel memory references based on explicit array declarations in the source code. We consider the need to synthesize not only array references but also memory operations targeting pointers and dynamic data structures. This paper describes Automatic Memory Partitioning, a method for automatically synthesizing general data structures (arrays and pointers) into multiple memory banks for increased parallelism and performance. We use source code instrumentation to collect memory traces in order to detect linear memory access patterns. The memory traces are used to split data structures into disjoint memory regions and determine which segments may benefit from parallel memory access. We present an algorithm for allocating memory segments into multiple memory banks. Experiments show significant improvements in performance while conserving the number of memory banks.

关键词： Design Algorithms Performance reconfigurable computing memory analysis memory banks

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ROC: A reconfigurable Optical Computer for Simulating Physical Processes

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acm transactions ON PARALLEL COMPUTING 2020年第1期7卷 1–29页

作者： Anderson, Jeff Kayraklioglu, Engin Sun, Shuai Crandall, Joseph Alkabani, Yousra Narayana, Vikram Sorger, Volker El-Ghazawi, Tarek George Washington Univ 800 22nd St NW5000 Sci & Engn Hall Washington DC 20052 USA Halmstad Univ Halmstad Sweden Intel Corp Santa Clara CA 95051 USA

Due to the end of Moore's law and Dennard scaling, we are entering a new era of processors. Computing systems are increasingly facing power and performance challenges due to both device- and circuit-related challenges with resistive and capacitive charging. Non-von Neumann architectures are needed to support future computations through innovative post-Moore's law architectures. To enable these emerging architectures with high-performance and at ultra-low power, both parallel computation and inter-node communication on-the-chip can be supported using photons. To this end, we introduce ROC, a reconfigurable optical computer that can solve partial differential equations (PDEs). PDE solvers form the basis for many traditional simulation problems in science and engineering that are currently performed on supercomputers. Instead of solving problems iteratively, the proposed engine uses a resistive mesh architecture to solve a PDE in a single iteration (one-shot). Instead of using actual electrical circuits, the physical underlying hardware emulates such structures using a silicon-photonics mesh that splits light into separate pathways, allowing it to add or subtract optical power analogous to programmable resistors. The time to obtain the PDE solution then only depends on the time-of-flight of a photon through the programmed mesh, which can be on the order of 10's of picoseconds given the millimeter-compact integrated photonic circuit. Numerically validated experimental results show that, over multiple configurations, ROC can achieve several orders of magnitude improvement over state-of-the-art GPUs when speed, power, and size are taken into account. Further, it comes within approximately 90% precision of current numerical solvers. As such, ROC can be a viable reconfigurable, approximate computer with the potential for more precise results when replacing silicon-photonics building blocks with nanoscale photonic lumped-elements.

关键词： PDE solver accelerator approximate computing nanophotonic computing analog computing optical computing post-Moore's law processors

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From silicon to science: The long road to production reconfigurable supercomputing

From silicon to science: The long road to production reconfi...

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作者： Underwood, Keith D. Hemmert, K. Scott Ulmer, Craig D. Intel Corporation P.O. Box 5200 MS-1319 Albuquerque NM 87185-1319 United States Sandia National Labs P.O. Box 5800 Albuquerque NM 87185-1319 United States

The field of high performance computing (HPC) currently abounds with excitement about the potential of a broad class of things called accelerators. And, yet, few accelerator based systems are being deployed in general purpose HPC environments. Why is that? This article explores the challenges that accelerators face in the HPC world, with a specific focus on FPGA based systems. We begin with an overview of the characteristics and challenges of typical HPC systems and applications and discuss why FPGAs have the potential to have a significant impact. The bulk of the article is focused on twelve specific areas where FPGA researchers can make contributions to hasten the adoption of FPGAs in HPC environments. © 2009 acm 1936-7406/2009/09-ART26.

关键词： Field programmable gate arrays (FPGA)

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Auto-Tuning CNNs for Coarse-Grained reconfigurable Array-Based Accelerators

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2018年第11期37卷 2301-2310页

作者： Bae, Inpyo Harris, Barend Min, Hyemi Egger, Bernhard Seoul Natl Univ Dept Comp Sci & Engn Seoul 08826 South Korea

As more and more deep learning tasks are pushed to mobile devices, accelerators for running these networks efficiently gain in importance. We show a that an existing class of general purpose accelerators, modulo-scheduled coarse-grained reconfigurable array (CGRA) processors typically used to accelerate multimedia workloads, can be a viable alternative to dedicated deep neural network processing hardware. To this end, an auto-tuning compiler is presented that maps convolutional neural networks (CNNs) efficiently on such architectures. The auto-tuner analyzes the structure of the CNN and the features of the CGRA, then explores the large optimization space to generate code that allows for an efficient mapping of the network. Evaluated with various CNNs, the auto-tuned code achieves an 11-fold speedup over the initial mapping. Comparing the energy per interference, the CGRA outperforms other general-purpose accelerators and an ARMv8 processor by a significant margin.

关键词： Automatic code optimization coarse-grained reconfigurable array (CGRA) convolutional neural network (CNN) accelerator

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