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作者： Kim, Changmoo Chung, Mookyoung Cho, Yeongon Konijnenburg, Mario Ryu, Soojung Kim, Jeongwook Samsung Advanced Institute of Technology 130 Samsung-ro Yeongtonggu Suwon-si Gyeonggi-do 443-803 Korea Republic of Holst Centre High Tech Campus 31 5656 AE Eindhoven Netherlands Imec Kapeldreef 75 B-3001 Heverlee Belgium

The latest biomedical applications require low energy consumption, high performance, and wide energyperformance scalability to adapt to various working environments. In this study, we present ULP-SRP, an energy-efficient reconfigurable processor for biomedical applications. ULP-SRP uses a Coarse-Grained reconfigurable Array (CGRA) for high-performance data processing with low energy consumption. We adopted a compact-size CGRA and modified it to support dynamically switchable three performance modes with finegrained power gating in order to further optimize the energy consumption. The energy-performance scalability is also accomplished with multiple performance modes and a Unified Memory Architecture (UMA). Experimental results show that ULP-SRP achieved 59% energy reduction compared to previous works. A technique of dynamic CGRA mode changing gives 18.9% energy reduction. ULP-SRP is a good candidate for future mobile healthcare devices. © 2014 acm.

关键词： Memory architecture

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Operator-Defined reconfigurable Network OS for Software-Defined Networks

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IEEE-acm transactions ON NETWORKING 2019年第3期27卷 1206-1219页

作者： Nam, Jaehyun Jo, Hyeonseong Kim, Yeonkeun Porras, Phillip Yegneswaran, Vinod Shin, Seungwon Korea Adv Inst Sci & Technol Grad Sch Informat Secur Daejeon 34141 South Korea Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea SRI Int SRIs Comp Sci Lab 333 Ravenswood Ave Menlo Pk CA 94025 USA SRI Int 333 Ravenswood Ave Menlo Pk CA 94025 USA

Barista is a novel architecture that seeks to enable flexible and customizable instantiations of network operating systems (NOSs) for software-defined networks (SDNs). As the NOS is the strategic control center of an SDN, implementing logic for management of network switches as well as higher-level applications, its design is critical to the welfare of the network. In this paper, we focus on three aspects of composable controller design: component synthesis, dynamic event control, and predictive NOS assessment. First, the modular design of the Barista enables flexible composition of functionalities prevalent in contemporary SDN controllers. Second, its event handling mechanism enables dynamic customization of control flows in a NOS. Third, its predictive NOS assessment helps to discover the optimal composition for the requirements specified by operators. These capabilities allow Barista operators to optimally select functionalities and dynamically handle events for their operating requirements while maximizing the resource utilization of the given system. Our results demonstrate that Barista can synthesize NOSs with many functionalities found in commodity controllers with competitive performance profiles.

关键词： Software-defined networking component synthesis dynamic event control predictive NOS assessment

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An application development framework for ARISE reconfigurable processors

An application development framework for ARISE reconfigurabl...

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作者： Vassiliadis, Nikolaos Theodoridis, George Nikolaidis, Spiridon Electronics and Computers Section Physics Department Aristotle University of Thessaloniki 54124 Thessaloniki Greece

Coupling reconfigurable hardware accelerators with processors is an effective way to meet the performance and flexibility required to cope with modern embedded applications. The ARISE framework provides a systematic approach to extend a processor once. It will thereafter support the coupling of arbitrary hardware accelerators. The accelerators can be coupled as coprocessors or functional units of the processor's datapath, and therefore exploited as a hybrid, which includes both loose and tight computational models. This article presents a complete framework for developing applications on such hybrid reconfigurable ARISE machines. The framework integrates the automatic identification of custom instructions and the semiautomatic/profiling-driven identification of coprocessors supporting the hybrid computational model. Moreover, it supports a modular design approach where the software and the hardware modules are developed independently and later ported into any ARISE machine with reconfigurable technology. To evaluate efficiency, a set of benchmarks is implemented on an ARISE evaluation machine utilizing the proposed framework. In addition, the ARISE machine is compared against a well-established processor paradigm that utilizes reconfigurable accelerators following only the typical coprocessor approach. Experimental results prove that the framework can be used to exploit the hybrid computational model and achieve significant performance improvements over the typical coprocessor acceleration approach. Moreover, results demonstrate how the framework can be used to trade off performance, silicon area, and application development time. © 2009 acm 1936-7406/2009/09-ART24.

关键词： Coprocessor

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Automatic Compilation to a Coarse-Grained reconfigurable System-opn-Chip

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acm transactions on Embedded Computing systems 2003年第4期2卷 560-589页

作者： Najjar, Walid Kurdahi, Fadi Bagherzadeh, Nader Bohm, Wim Hammes, Jeff Venkataramani, Girish Department of Computer Science and Engineering University of California Riverside Riverside CA 92521-0304 United States Department of EECS University of California Irvine Irvine United States Department of Computer Science Colorado State University Fort Collins CO United States SRC Corp. Colorado Springs United States Carnegie-Mellon University Department of Computer Science United States

The rapid growth of device densities on silicon has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, one of the obstacles to the wider acceptance of this technology is its programmability. The application needs to be programmed in hardware description languages or an assembly equivalent, whereas most application programmers are used to the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. The Morphosys project proposes an SoC architecture consisting of reconfigurable hardware that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and automatically map the application onto the Morphosys architecture. The mapping process is static and it involves operation scheduling, processor allocation and binding, and register allocation in the context of the Morphosys architecture. The compiler also handles issues concerning data streaming and caching in order to minimize data transfer overhead. We have compiled some important image-processing kernels, and the generated schedules reflect an average speedup in execution times of up to 6£ compared to the execution on 800 MHz Pentium III machines. © 2003, acm. All rights reserved.

关键词： Algorithms compilers Design Experimentation reconfigurable computing SIMD

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Multivariate Gaussian Random Number Generation Targeting reconfigurable Hardware

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acm transactions on reconfigurable technology and systems 2008年第2期1卷 1-29页

作者： Thomas, David B. Luk, Wayne Imperial College London United Kingdom

The multivariate Gaussian distribution is often used to model correlations between stochastic time-series, and can be used to explore the effect of these correlations across N time-series in Monte-Carlo simulations. However, generating random correlated vectors is an O(N²) process, and quickly becomes a computational bottleneck in software simulations. This article presents an efficient method for generating vectors in parallel hardware, using N parallel pipelined components to generate a new vector every N cycles. This method maps well to the embedded block RAMs and multipliers in contemporary FPGAs, particularly as extensive testing shows that the limited bit-width arithmetic does not reduce the statistical quality of the generated vectors. An implementation of the architecture in the Virtex-4 architecture achieves a 500MHz clock-rate, and can support vector lengths up to 512 in the largest devices. The combination of a high clockrate and parallelism provides a significant performance advantage over conventional processors, with an xc4vsx55 device at 500MHz providing a 200 times speedup over an Opteron 2.6GHz using an AMD optimised BLAS package. In a case study in Delta-Gamma Value-at Risk, an RC2000 accelerator card using an xc4vsx55 at 400MHz is 26 times faster than a quad Opteron 2.6GHz SMP. © 2008, acm. All rights reserved.

关键词： Algorithms Design Economics FPGA multivariate Gaussian distribution Random numbers

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Remarn: A reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks

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acm transactions on reconfigurable technology and systems 2023年第1期16卷 1-26页

作者： Que, Zhiqiang Nakahara, Hiroki Fan, Hongxiang Li, He Meng, Jiuxi Tsoi, Kuen Hung Niu, Xinyu Nurvitadhi, Eriko Luk, Wayne Imperial Coll London Exhibit Rd London SW7 2BX England Tokyo Inst Technol Ohokayama 1-21-2 Tokyo 1528550 Japan Univ Cambridge Cambridge CB2 1TN England Corerain Technol Ltd 14F Changfu Jinmao Bldg CFC Shenzhou Peoples R China Intel Corp Jones Farm Campus Hillsboro OR 97124 USA

This work introduces Remarn, a reconfigurable multi-threaded multi-core accelerator supporting both spatial and temporal co-execution of Recurrent Neural Network (RNN) inferences. It increases processing capabilities and quality of service of cloud-based neural processing units (NPUs) by improving their hardware utilization and by reducing design latency, with two innovations. First, a custom coarse-grained multi-threaded RNN/Long Short-Term Memory (LSTM) hardware architecture, switching tasks among threads when RNN computational engines meet data hazards. Second, the partitioning of this hardware architecture into multiple full-fledged sub-accelerator cores, enabling spatially co-execution of multiple RNN/LSTM inferences. These innovations improve the exploitation of the available parallelism to increase runtime hardware utilization and boost design throughput. Evaluation results show that a dual-threaded quad-core Remarn NPU achieves 2.91 times higher performance while only occupying 5.0% more area than a single-threaded one on a Stratix 10 FPGA. When compared with a Tesla V100 GPU implementation, our design achieves 6.5 times better performance and 15.6 times higher power efficiency, showing that our approach contributes to high performance and energy-efficient FPGA-based multi-RNN inference designs for datacenters.

关键词： Accelerator architecture recurrent neural networks multi-tenant execution

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Accelerating Attention Mechanism on FPGAs based on Efficient reconfigurable Systolic Array

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acm transactions ON EMBEDDED COMPUTING systems 2023年第6期22卷 1-22页

作者： Ye, Wenhua Zhou, Xu Zhou, Joey Chen, Cen Li, Kenli Hunan Univ Coll Informat Sci & Engn 2 Lushan South Rd Changsha 410082 Hunan Peoples R China China Elect Technol Grp Corp Res Inst 36 387 Hongxin Rd Jiaxing 314033 Zhejiang Peoples R China ASTAR Ctr Frontier AI Res 1 Fusionopolis Way08-01 Connexis Singapore 138632 Singapore Hunan Univ Shenzhen Inst Shenzhen Hightech Ind Pk South Dist Virtual Univ Shenzhen 518000 Guangdong Peoples R China

Transformer model architectures have recently received great interest in natural language, machine translation, and computer vision, where attention mechanisms are their building blocks. However, the attention mechanism is expensive because of its intensive matrix computations and complicated data flow. The existing hardware architecture has some disadvantages for the computing structure of attention, such as inflexibility and low efficiency. Most of the existing papers accelerate attention by reducing the amount of computation through various pruning algorithms, which will affect the results to a certain extent with different sparsity. This paper proposes the hardware accelerator for the multi-head attention (MHA) on field-programmable gate arrays (FPGAs) with reconfigurable architecture, efficient systolic array, and hardware-friendly radix-2 softmax. We propose a novel method called Four inputs Processing Element (FPE) to double the computation rate of the data-aware systolic array (SA) and make it efficient and load balance. Especially, the computation framework is well designed to ensure the utilization of SA efficiently. Our design is evaluated on a Xilinx Alveo U250 card, and the proposed architecture achieves 51.3x, 17.3x improvement in latency, and 54.4x, 17.9x energy savings compared to CPU and GPU.

关键词： Transformer attention FPGA reconfigurable systolic array softmax Accelerator

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Introduction to the Special Issue on the 7th International Workshop on reconfigurable Communication-centric systems-on-Chip (ReCoSoC'12)

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acm transactions on reconfigurable technology and systems 2014年第3期7卷 1页

作者： Voros, Nikolaos Gogniat, Guy Technol Educ Inst Western Greece Athens Greece

No abstract available.

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Extending UML/MARTE to support discrete controller synthesis, application to reconfigurable systems-on-chip modeling

Extending UML/MARTE to support discrete controller synthesis...

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作者： Guillet, Sébastien De Lamotte, Florent Le Griguer, Nicolas Rutten, Éric Gogniat, Guy Diguet, Jean-Philippe Lab-STICC Rue de Saint-Maude 56100 Lorient France INRIA Rhone-Alpes UMR 5217-Laboratoire LIG-Maison Universitaire de Saint-Martin D' Heres-BP Jean Kuntzmann-110 av. de la Chimie-Domaine 53-38041 Grenoble cedex 9 France

This article presents the first framework to design and synthesize a formal controller managing dynamic reconfiguration, using a model-driven engineering methodology based on an extension of UML/MARTE. The implementation technique highlights the combination of hard configuration constraints using weights (control part)-ensured statically and fulfilled by the system at runtime-and soft constraints (decision part) that, given a set of correct and accessible configurations, choose one of them. An application model of an image processing application is presented, then transformed and synthesized to be executed on a Xilinx platform to show how the controller, executed on a Microblaze, manages the hardware reconfigurations. © 2014 acm.

关键词： Controllers

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A variable-grain logic cell and routing architecture for a reconfigurable IP core

A variable-grain logic cell and routing architecture for a r...

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作者： Inoue, Kazuki Zhao, Qian Okamoto, Yasuhiro Yosho, Hiroki Amagasaki, Motoki Iida, Masahiro Sueyoshi, Toshinori Graduate School of Science and Technology Kumamoto University Japan

In the present study, we investigate the use of reconfigurable logic devices (RLDs) as intellectual properties (IPs) for system on a chip (SoC). Using RLDs, SoCs can achieve both high performance and high flexibility. However, conventional RLDs have problems related to performance, area, and power consumption. In order to resolve these problems, we investigated the features of RLD architecture. RLDs are classified into fine-grained and coarse-grained devices based on their architecture. Generally, the granularity of an RLD is limited to either type, which means that a device can only achieve high performance in applications that are suited to its architecture. Therefore, we propose a variable-grain logic cell (VGLC) architecture that can overcome the trade-off between fine-grained and coarse-grained architectures, which are required for the implementation of random and arithmetic logics, respectively. The VGLC is based on a 4-bit adder including configuration bits, which can perform arithmetic and random logic operations unlike the LUT. In the present paper, a local interconnection architecture for the VGLC is proposed. Several types of local interconnections composed of different crossbars are compared, and the trade-off between hardware resources and flexibility is discussed. Using local interconnection, the routing area is reduced by a maximum of 49%. © 2010 acm.

关键词： Logic devices

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