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A Retargetable Compilation Framework for Heterogeneous reconfigurable Computing

acm transactions on reconfigurable technology and systems 2016年第4期9卷 24-24页

作者： Ul-Abdin, Zain Svensson, Bertil Halmstad Univ Sch Informat Technol CERES POB 823 SE-30118 Halmstad Sweden

The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable interconnection network. However, the mastering of low-level microarchitectural details involved in the programming of such massively parallel platforms becomes too cumbersome, which limits their adoption in many applications. Thus, there is a dire need for an approach to produce high-performance scalable implementations that harness the computational resources of the emerging reconfigurable platforms. This article addresses the grand challenge of accessibility of these diverse reconfigurable platforms by suggesting the use of a high-level language, occam-pi, and developing a complete design flow for building, compiling, and generating machine code for heterogeneous coarse-grained hardware. We have evaluated the approach by implementing complex industrial case studies and three common signal processing algorithms. The results of the implemented case studies suggest that the occam-pi language-based approach, because of its well-defined semantics for expressing concurrency and reconfigurability, simplifies the development of applications employing runtime reconfigurable devices. The associated compiler framework ensures portability as well as the performance benefits across heterogeneous platforms. CCS Concepts: . Computer systems organization -> reconfigurable computing;Heterogeneous (hybrid) systems;. Software and its engineering -> Retargetable compilers

关键词： reconfigurable processor arrays runtime reconfiguration compiler frameworks occam-pi

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A Bimodal Scheduler for Coarse-Grained reconfigurable Arrays

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acm transactions ON ARCHITECTURE AND CODE OPTIMIZATION 2016年第2期13卷 15-15页

作者： Theocharis, Panagiotis De Sutter, Bjorn Univ Ghent Comp Syst Lab Technol Pk Zwijnaarde 15 B-9052 Ghent Belgium

Compilers for Course-Grained reconfigurable Array (CGRA) architectures suffer from long compilation times and code quality levels far below the theoretical upper bounds. This article presents a new scheduler, called the Bimodal Modulo Scheduler (BMS), to map inner loops onto (heterogeneous) CGRAs of the Architecture for Dynamically reconfigurable Embedded systems (ADRES) family. BMS significantly outperforms existing schedulers for similar architectures in terms of generated code quality and compilation time. This is achieved by combining new schemes for backtracking with extended and adapted forms of priority functions and cost functions, as described in the article. BMS is evaluated by mapping multimedia and software-defined radio benchmarks onto tuned ADRES instances.

关键词： Architecture Compiler Performance Modulo scheduling placement and routing cost functions

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Simulating reconfigurable Multiprocessor systems-on-Chip with MPSoCSim

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acm transactions ON EMBEDDED COMPUTING systems 2016年第1期16卷 4-4页

作者： Wehner, Philipp Rettkowski, Jens Kalb, Tobias Goehringer, Diana Ruhr Univ Bochum MCA Applicat Specif Multicore Architectures Grp Bldg IDFloor 1Room 347Univ Str 150 D-44780 Bochum Germany

Upcoming reconfigurable Multiprocessor systems-on-Chip (MPSoCs) present new challenges for the design and early estimation of technology requirements due to their runtime adaptive hardware architecture. The usage of simulators offers capabilities to overcome these issues. In this article, MPSoCSim, a SystemC simulator for Network-on-Chip (NoC) based MPSoCs is extended to support the simulation of reconfigurable MPSoCs. Processors, such as ARM and MicroBlaze, and peripheral models used within the virtual platform are provided by Imperas/OVP and attached to the NoC. Moreover, traffic generators are available to analyze the system. The virtual platform currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First algorithm, and an adaptive West-First algorithm. Amongst the impact of routing algorithms regarding performance, reconfiguration processes can be examined using the presented simulator. A mechanism for dynamic partial reconfiguration is implemented that is oriented towards the reconfiguration scheme on real FPGA platforms. It includes the simulation of the undefined behavior of the hardware region during reconfiguration and allows the adjustment of parameters. During runtime, dynamic partial reconfiguration interfaces are used to connect the Network-on-Chip infrastructure with reconfigurable regions. The configuration access ports can be modeled by the controller for the dynamic partial reconfiguration in form of an application programming interface. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator timing and power consumption of the simulated hardware are estimated and compared with a real hardware implementation on a Xilinx Zynq FPGA. The comparison shows that the simulator improves the development of reconfigurable MPSoCs by early estimation of system requirements. The power estimations show a maximum deviation of 9m

关键词： MPSoC simulator network-on-chip dynamic partial reconfiguration heterogeneous MPSoC reconfigurable computing routing algorithms OVP virtual platform

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A reconfigurable Architecture for the Detection of Strongly Connected Components

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acm transactions on reconfigurable technology and systems 2016年第2期9卷 16-16页

作者： Attia, Osama G. Townsend, Kevin R. Jones, Phillip H. Zambreno, Joseph Iowa State Univ Dept Elect & Comp Engn RCL Ames IA 50010 USA

The Strongly Connected Components (SCCs) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this article, we investigate the design of a parallel hardware architecture for the detection of SCCs in directed graphs. We propose a design methodology that alleviates memory latency and problems with irregular memory access. The design is composed of 16 processing elements dedicated to parallel Breadth-First Search (BFS) and eight processing elements dedicated to finding intersection in parallel. Processing elements are organized to reuse resources and utilize memory bandwidth efficiently. We demonstrate a prototype of our design using the Convey HC-2 system, a commercial high-performance reconfigurable computing coprocessor. Our experimental results show a speedup of as much as 17x for detecting SCCs in large-scale graphs when compared to a conventional sequential software implementation.

关键词： Design Algorithms Performance Breadth-first search strongly connected components convey HC-2 FPGA applications graphs reconfigurable computing

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FPGA-Based Dynamically reconfigurable SQL Query Processing

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acm transactions on reconfigurable technology and systems 2016年第4期9卷 25-25页

作者： Ziener, Daniel Bauer, Florian Becher, Andreas Dennl, Christopher Meyer-Wegener, Klaus Schuerfeld, Ute Teich, Juergen Vogt, Joerg-Stephan Weber, Helmut Univ Erlangen Nurnberg Cauerstr 11 D-91058 Erlangen Germany Univ Erlangen Nurnberg Martensstr 3 D-91058 Erlangen Germany IBM Deutschland Res & Dev GmbH Schonaicher Str 220 D-71032 Boblingen Germany Hamburg Univ Technol TUHH Schwarzenberg Campus 3 E D-21073 Hamburg Germany

In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row-as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined. Categories and Subject Descriptors: B.5.1 [Register-Transfer-Level Implementation]: Design-Data-path design;C.3 [Special-Purpose and Application-based systems]: Microprocessor/Microcomputer Applications;H.2.4 [Database Management]: systems-Query processing

关键词： Design Performance FPGA dynamic partial reconfiguration SQL processing reconfigurable computing

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Analysis of Fixed, reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics

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acm transactions on reconfigurable technology and systems 2016年第1期10卷 2-2页

作者： Richardson, Justin George, Alan Cheng, Kevin Lam, Herman Univ Florida NSF Ctr High Performance Reconfigurable Comp CHRE 2033 Mowry RD Room 119POB 103610 Gainesville FL 32611 USA Univ Florida NSF CHREC Ctr ECE Dept Room 320Larsen Hall968 Ctr DrPOB 116200 Gainesville FL 32611 USA

The modern processor landscape is a varied and diverse community. As such, developers need away to quickly and fairly compare various devices for use with particular applications. This article expands the authors' previously published computational-density metrics and presents an analysis of a new generation of various device architectures, including CPU, DSP, FPGA, GPU, and hybrid architectures. Also, new memory metrics are added to expand the existing suite of metrics to characterize the memory resources on various processing devices. Finally, a new relational metric, realizable utilization (RU), is introduced, which quantifies the fraction of the computational density metric that an application achieves within an individual implementation. The RU metric can be used to provide valuable feedback to application developers and architecture designers by highlighting the upper bound on specific application optimization and providing a quantifiable measure of theoretical and realizable performance. Overall, the analysis in this article quantifies the performance tradeoffs among the architectures studied, the memory characteristics of different device types, and the efficiency of device architectures.

关键词： Device characterization benchmarking performance device studies comparative analysis

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A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing

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acm transactions on reconfigurable technology and systems 2016年第1期10卷 1-1页

作者： Wulf, Nicholas George, Alan D. Gordon-Ross, Ann Univ Florida NSF Ctr High Performance Reconfigurable Comp CHRE POB 116200 Gainesville FL 32611 USA Univ Florida 968 Ctr Dr Gainesville FL 32611 USA Univ Florida POB 116200 Gainesville FL 32611 USA

On-board processing systems are often deployed in harsh aerospace environments and must therefore adhere to stringent constraints such as low power, small size, and high dependability in the presence of faults. Field-programmable gate arrays (FPGAs) are often an attractive option for designers seeking low-power, high-performance devices. However, unlike nonreconfigurable devices, radiation effects can alter an FPGA's functionality instead of just the device's data, requiring designers to consider fault-tolerant strategies to mitigate these effects. In this article, we present a framework to ease these system design challenges and aid designers in considering a broad range of devices and fault-tolerant strategies for on-board processing, highlighting the most promising options and tradeoffs early in the design process. This article focuses on the power, dependability, and lifetime evaluation metrics, which our framework calculates and leverages to evaluate the effectiveness of varying system-on-chip (SoC) designs. Finally, we use our framework to evaluate SoC designs for a case study on a hyperspectral-imaging (HSI) mission to demonstrate our framework's ability to identify efficient and effective SoC designs.

关键词： Aerospace fault-tolerant FPGA Pareto optimal single-event upset system design

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Dynamic Task Mapping with Congestion Speculation for reconfigurable Network-on-Chip

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acm transactions on reconfigurable technology and systems 2016年第1期10卷 3-3页

作者： Chao, Hung-Lin Tung, Sheng-Ya Hsiung, Pao-Ann Natl Chung Cheng Univ Dept Comp Sci & Informat Engn 168 Univ Rd Chiayi 62102 Taiwan

Network-on-Chip (NoC) has been proposed as a promising communication architecture to replace the dedicated interconnections and shared buses for future embedded system platforms. In such a parallel platform, mapping application tasks to the NoC is a key issue because it affects throughput significantly due to the problem of communication congestion. Increased communication latency, low system performance, and low resource utilization are some side-effects of a bad mapping. Current mapping algorithms either do not consider link utilizations or consider only the current utilizations. Besides, to design an efficient NoC platform, mapping task to computation nodes and scheduling communication should be taken into consideration. In this work, we propose an efficient algorithm for dynamic taskmapping with congestion speculation (DTMCS) that not only includes the conventional application mapping, but also further considers future traffic patterns based on the link utilization. The proposed algorithm can reduce overall congestion, instead of only improving the current packet blocking situation. Our experiment results have demonstrated that compared to the state-of-the-art congestion-aware Path Load algorithm, the proposed DTMCS algorithm can reduce up to 40.5% of average communication latency, while the maximal communication latency can be reduced by up to 67.7%.

关键词： Network-on-chip application mapping task mapping congestion speculation

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Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs

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acm transactions on reconfigurable technology and systems 2016年第2期9卷 11-11页

作者： Kashyap, Hirak Chaves, Ricardo Univ Lisbon INESC ID IST Rua Alves Redol 9 P-1000029 Lisbon Portugal

The dynamic partial reconfiguration functionality of FPGAs can be attacked, particularly when the FPGA is remotely located or the configuration bitstreams are sent through insecure networks. The existing FPGA technologies provide some built-in security mechanisms;however, these are often inadequate. The existing solutions still impose a significant impact on the reconfiguration process and on the available resources. This article proposes a solution to improve the security of dynamic partial reconfiguration of FPGAs, without significantly affecting the reconfiguration performance. The proposed solution changes the encryption key of the remotely received bitstream by a randomly generated key, unique for each configuration, when storing them in the external unsecured memory. The native frame-wise error detection mechanism combined with an additional CBC-MAC authentication mechanism, allows for an improved countermeasure against replay attack and wrongful bitstream usage. The proposed solution introduces an overhead of 1% of the available resources on the target FPGA and provides the lowest impact on the reconfiguration process when compared to the state of the art, achieving a reconfiguration throughput of 2.5Gbps. Regarding the built-in security mechanism provided by the Xilinx FPGAs, the solution herein proposed provides better security and improves the reconfiguration performance by more than 3 times.

关键词： Security Design and Performance Bitstream encryption bitstream security reconfigurable architectures secure dynamic partial reconfiguration and system downgrade prevention

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ODoST: Automatic Hardware Acceleration for Biomedical Model Integration

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acm transactions on reconfigurable technology and systems 2016年第4期9卷 27-27页

作者： Yu, Ting Bradley, Chris Sinnen, Oliver Univ Auckland Dept Elect & Comp Engn Private Bag 92019 Auckland 1142 New Zealand Univ Auckland Auckland Bioengn Inst Level 670 Symonds St Auckland New Zealand

Dynamic biomedical systems are mathematically described by Ordinary Differential Equations (ODEs) and their solution is often one of the most computationally intensive parts in biomedical simulations. With high inherent parallelism, hardware acceleration based on Field-Programmable Gate Arrays (FPGAs) has great potential to increase the computational performance of the model simulations, while being very power-efficient. However, the manual hardware implementation is complex and time consuming. The advantages of FPGA designs can only be realised if there is a general solution to automate the process. In this article, we propose a domain-specific high-level synthesis tool called ODoST that automatically generates an FPGA-based Hardware Accelerator Module (HAM) from a high-level description. In this direct approach, ODE equations are directly mapped to processing pipelines without any intermediate architecture layer of processing elements. We evaluate the generated HAMs on real hardware based on their resource usage, processing speed, and power consumption, and compare them with CPUs and a GPU. The results show that FPGA implementations can achieve 15.3 times more speedup compared to a single core CPU solution and perform similarly to an auto-generated GPU solution, while the FPGA implementations can achieve 14.5 times more power efficiency than the CPU and 3.1 times compared to the optimised GPU solution. Improved speedups are foreseeable based on further optimisations. Categories and Subject Descriptors: C.1.3 [Processor Architectures]: Other Architecture Styles-Styles-Heterogeneous (hybrid) systems;Pipeline processors

关键词： Design Algorithms Performance High-performance reconfigurable computing high-level synthesis biomedical modeling

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