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作者： Brugger, Christian Hillenbrand, Dominic Balzer, Matthias Microelectronic Systems Design Research Group University of Kaiserslautern Germany Green Computing Systems Research and Development Center Department of Computer Science and Engineering Waseda University Tokyo Japan Institute for Data Processing and Electronics Karlsruhe Institute of Technology Germany

For high-performance embedded hard-real-time systems, ASICs and FPGAs hold advantages over generalpurpose processors and graphics accelerators (GPUs). However, developing signal processing architectures from scratch requires significant resources. Our design methodology is based on sets of configurable building blocks that provide storage, dataflow, computation, and control. Based on our building blocks, we generate hundreds of thousands of our dynamic streaming engine processors that we call DSEs. We store our DSEs in a repository that can be queried for (online) design space exploration. From this repository, DSEs can be downloaded and instantiated within milliseconds on FPGAs. If a loss of flexibility can be tolerated then ASIC implementations are feasible as well. In this article we focus on FPGA implementations. Our DSEs vary in cores, computational lanes, bitwidths, power consumption, and frequency. To the best of our knowledge we are the first to propose online design space exploration based on repositories of precompiled cores that are assembled of common building blocks. For demonstration purposes we map algorithms for image processing and financial mathematics to DSEs and compare the performance to existing highly optimized signal and graphics accelerators. © 2014 acm.

关键词： Field programmable gate arrays (FPGA)

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Design assurance strategy and toolset for Partially reconfigurable FPGA systems

Design assurance strategy and toolset for Partially Reconfig...

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作者： Kȩpa, K. Morgan, F. Kościuszkiewicz, K. Braun, L. Hübner, M. Becker, J. Electrical and Electronic Engineering National University of Ireland Galway Ireland Karlsruhe Germany

The growth of the reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools. This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic frontend allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by "recipe" scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system. The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs. © 2010 acm.

关键词： Field programmable gate arrays (FPGA)

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Optimal loop unrolling and shifting for reconfigurable architectures

Optimal loop unrolling and shifting for reconfigurable archi...

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作者： Dragomir, Ozana Silvia Stefanov, Todor Bertels, Koen Computer Engineering Laboratory TU Delft Mekelweg 4 2628CD Delft Netherlands

In this article, we present a new technique for optimizing loops that contain kernels mapped on a reconfigurable fabric. We assume the Molen machine organization as our framework. We propose combining loop unrolling with loop shifting, which is used to relocate the function calls contained in the loop body such that in every iteration of the transformed loop, software functions (running on GPP) execute in parallel with multiple instances of the kernel (running on FPGA). The algorithm computes the optimal unroll factor and determines the most appropriate transformation (which can be the combination of unrolling plus shifting or either of the two). This method is based on profiling information about the kernel's execution times on GPP and FPGA, memory transfers and area utilization. In the experimental part, we apply this method to several kernels from loop nests extracted from real-life applications (DCT and SAD from MPEG2 encoder, Quantizer from JPEG, and Sobel's Convolution) and perform an analysis of the results, comparing them with the theoretical maximum speedup by Amdahl's Law and showing when and how our transformations are beneficial. © 2009 acm 1936-7406/2009/09-ART25.

关键词： Field programmable gate arrays (FPGA)

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FRL: Fast and reconfigurable Accelerator for Distributed Sound Source Localization

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2022年第11期41卷 3922-3933页

作者： Ding, Xiaofeng Wang, Chengliang Liu, Heping Zhang, Zhihai Chen, Xianzhang Tan, Yujuan Liu, Duo Ren, Ao Chongqing Univ Coll Comp Sci Chongqing 400030 Peoples R China Chongqing Univ Coll Optoelect Engn Chongqing 400030 Peoples R China

Sound source localization (SSL) has been widely applied in industrial and civil fields. And with the development of wearable devices and the Internet of Things (IoT), it is attractive to deploy the SSL system onto embedded and portable devices. However, the software-based SSL system causes excessive response delay and is often affected by environmental noise. To overcome this obstacle, we propose the fast and precise localization (FPL) algorithm for distributed SSL systems. It combines the benefits of both time difference of arrival (TDOA) and steered response power (SRP) methods, and thus it is able to localize sound sources fast and precisely. To further improve the localization speed, we propose the fast and reconfigurable localization (FRL) accelerator, which is an algorithm-hardware co-designed SSL accelerator. It adopts multiple distributed localization nodes for higher localization precision and higher robustness to environmental interference, and it can be configured into either the fast or precise mode to adapt to various environments. Experimental evaluations show that our proposed FPL algorithm can achieve high localization speed and precision, and the field-programmable gate array (FPGA)-based FRL accelerator outperforms the software implementation by 48.6x and outperforms the prior FPGA-based SSL accelerators by 20x similar to 838.2x.

关键词： Field-programmable gate array (FPGA) reconfigurable architecture software-hardware co-design sound source localization (SSL)

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Exploring reconfigurable architectures for tree-based option pricing models

Exploring reconfigurable architectures for tree-based option...

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作者： Jin, Qiwei Thomas, David B. Luk, Wayne Cope, Benjamin Department of Computing Imperial College 180 Queen's Gate London SW7 2AZ United Kingdom Circuits and Systems Group Department of Electrical and Electronic Engineering Imperial College 180 Queen's Gate London SW7 2AZ United Kingdom

This article explores the application of reconfigurable hardware to the acceleration of financial computation using tree-based pricing models. Two parallel pipelined architectures have been developed for option valuation using binomial trees and trinomial trees, with support for concurrent evaluation of independent options to achieve high pricing throughput. Our results show that the tree-based models executing on a Virtex 4 field programmable gate array (FPGA) at 82.7 MHz with fixed-point arithmetic can run over 160 times faster than a Core2 Duo processor at 2.2 GHz. The FPGA implementation is two times faster than the nVidia Geforce 7900GTX processor with 24 pipelines at 650 MHz, and 27%-35% slower than the nVidia Geforce 8600GTS processor with 32 Pipelines at 1450 MHz. Our preliminary experiments also indicate that while an FPGA implementation can be slower than a GPU, it could be more efficient when power consumption is taken into account. © 2009 acm 1936-7406/2009/09-ART21.

关键词： Pipelines

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UNILOGIC: A novel architecture for highly parallel reconfigurable systems

UNILOGIC: A novel architecture for highly parallel reconfigu...

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acm transactions on reconfigurable technology and systems

作者： Ioannou, Aggelos D. Georgopoulos, Konstantinos Malakonakis, Pavlos Pnevmatikatos, Dionisios N. Papaefstathiou, Vassilis D. Papaefstathiou, Ioannis Mavroidis, Iakovos School of ECE Technical University of Crete Telecommunication Systems Institute Crete Greece Telecommunication Systems Institute Chania Greece Chalmers University of Technology Gothenburg Sweden School of ECE Aristotle University of Thessaloniki Thessaloniki Greece

One of the main characteristics of High-performance Computing (HPC) applications is that they become increasingly performance and power demanding, pushing HPC systems to their limits. Existing HPC systems have not yet reached exascale performance mainly due to power limitations. Extrapolating from today's top HPC systems, about 100-200 MWatts would be required to sustain an exaflop-level of performance. A promising solution for tackling power limitations is the deployment of energy-efficient reconfigurable resources (in the form of Field-programmable Gate Arrays (FPGAs)) tightly integrated with conventional CPUs. However, current FPGA tools and programming environments are optimized for accelerating a single application or even task on a single FPGA device. In this work, we present UNILOGIC (Unified Logic), a novel HPC-tailored parallel architecture that efficiently incorporates FPGAs. UNILOGIC adopts the Partitioned Global Address Space (PGAS) model and extends it to include hardware accelerators, i.e., tasks implemented on the reconfigurable resources. The main advantages of UNILOGIC are that (i) the hardware accelerators can be accessed directly by any processor in the system, and (ii) the hardware accelerators can access any memory location in the system. In this way, the proposed architecture offers a unified environment where all the reconfigurable resources can be seamlessly used by any processor/operating system. The UNILOGIC architecture also provides hardware virtualization of the reconfigurable logic so that the hardware accelerators can be shared among multiple applications or tasks. The FPGA layer of the architecture is implemented by splitting its reconfigurable resources into (i) a static partition, which provides the PGAS-related communication infrastructure, and (ii) fixed-size and dynamically reconfigurable slots that can be programmed and accessed independently or combined together to support both fine and coarse grain reconfiguration.1 Finally, t

关键词： reconfigurable hardware Computation theory Computer hardware Energy efficiency Field programmable gate arrays (FPGA) Memory architecture Parallel architectures Program processors reconfigurable architectures Signal receivers System on chip Communication infrastructure Hardware virtualization High performance computing (HPC) Partitioned Global Address Space Programming environment Proposed architectures reconfigurable resources reconfigurable systems

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A Novel Attack Mode on Advanced technology Nodes Exploiting Transistor Self-Heating

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2022年第11期41卷 4134-4144页

作者： Rangarajan, Nikhil Knechtel, Johann Limaye, Nimisha Sinanoglu, Ozgur Amrouch, Hussam New York Univ Abu Dhabi Div Engn Abu Dhabi U Arab Emirates NYU Tandon Sch Engn Dept Elect & Comp Engn Brooklyn NY 11201 USA Univ Stuttgart Elect Engn Fac Chair Semicond Test & Reliabil Comp Sci D-70569 Stuttgart Germany

Self-heating (SH) is a phenomenon that can induce excessive heat inside the transistor channel. SH represents an emerging and serious concern, especially in advanced technology nodes, where excessive heat acting on elevated channel geometries will notably shift the critical transistor parameters (e.g., threshold-voltage V-th and carrier mobility mu). The underlying 3-D device structures (e.g., FinFET, nanowire, or nanosheet structures), along with newly employed materials such as silicon-germanium (SiGe), which show worse thermal conductivity than traditional materials, can considerably exacerbate SH. On top of that, quantum confinement, a phenomenon that becomes dominant at sub-10nm, further increases the intensity of SH. In this article, we are the first to explore SH effects from the perspective of hardware security, rather than the performance, reliability standpoints covered in state-of-the-art (SOTA) work. As proof of concept, we devise an SH-based hardware trojan (HT) that exploits the SH-induced V-th change in 7-nm FinFET circuits. Leveraging V-th-dependent reconfigurable logic, we design a reconfigurable HT payload that maliciously changes its functional behavior once the SH-induced V-th change takes effect. Following SOTA work, we present a comprehensive modeling and analysis of SH effects at the device level and highlight its impact on transistor V-th. Next, we study how fabrication-time changes in the transistor doping and geometry can promote the SH-assisted degradation. We then describe various payload configurations for the proposed HT, quantify its overheads, and discuss its resilience against standard HT detection techniques. Finally, we demonstrate two case studies using the proposed HT, one to leak the secret key from a pipelined design of an advanced encryption standard (AES) circuit, and another to showcase denial-of-service for a Gaussian-blur filter circuit. Our work utilizes industrystandard models with parameters extracted from measurements

关键词： Advanced encryption standard (AES) hardware trojan (HT) reconfigurable logic self-heating (SH) transistor aging

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Introduction to the Special Section on 19th reconfigurable Architectures Workshop (RAW 2012)

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acm transactions on reconfigurable technology and systems 2013年第2期6卷 1页

作者： Goehringer, Diana Cumplido, Rene Ruhr Univ Bochum Bochum Germany Natl Inst Astrophys Opt & Elect Mexico City DF Mexico

No abstract available.

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Keep in Balance: Runtime-reconfigurable Intermittent Deep Inference

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acm transactions on Embedded Computing systems 2023年第5 s期22卷 1-25页

作者： Yen, Chih-Hsuan Mendis, Hashan Roshantha Kuo, Tei-Wei Hsiu, Pi-Cheng Department of Computer Science and Information Engineering National Taiwan University Taiwan Academia Sinica Taiwan Mohamed Bin Zayed University of Artificial Intelligence United Arab Emirates College of Electrical Engineering and Computer Science National Taiwan University Taiwan Department of Computer Science and Information Engineering National Chi Nan University Taiwan

Intermittent deep neural network (DNN) inference is a promising technique to enable intelligent applications on tiny devices powered by ambient energy sources. Nonetheless, intermittent execution presents inherent challenges, primarily involving accumulating progress across power cycles and having to refetch volatile data lost due to power loss in each power cycle. Existing approaches typically optimize the inference configuration to maximize data reuse. However, we observe that such a fixed configuration may be significantly inefficient due to the fluctuating balance point between data reuse and data refetch caused by the dynamic nature of ambient *** work proposes DynBal, an approach to dynamically reconfigure the inference engine at runtime. DynBal is realized as a middleware plugin that improves inference performance by exploring the interplay between data reuse and data refetch to maintain their balance with respect to the changing level of intermittency. An indirect metric is developed to easily evaluate an inference configuration considering the variability in intermittency, and a lightweight reconfiguration algorithm is employed to efficiently optimize the configuration at runtime. We evaluate the improvement brought by integrating DynBal into a recent intermittent inference approach that uses a fixed configuration. Evaluations were conducted on a Texas Instruments device with various network models and under varied intermittent power strengths. Our experimental results demonstrate that DynBal can speed up intermittent inference by 3.26 times, achieving a greater improvement for a large network under high intermittency and a large gap between memory and computation performance. © 2023 Copyright held by the owner/author(s). Publication rights licensed to acm.

关键词： Deep neural networks

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PVoT: reconfigurable Photovoltaic Array for Indoor Light Energy-Powered Batteryless Devices

PVoT: Reconfigurable Photovoltaic Array for Indoor Light Ene...

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acm/IEEE Int Conf on Hardware/Software Codesign and Syst Synthesis / Int Conf on Compilers, Architectures, and Synthesis for Embedded Syst / Int Conf on Embedded Software part of the Embedded Syst Week

作者： Kim, Jiwon Kim, Eunyeong Jeon, Seunghyeok Ahn, Junick Jun, Hyungchol Cha, Hojung Yonsei Univ Dept Comp Sci Seoul 03722 South Korea

Multiple photovoltaic (PV) modules are often used to provide enhanced harvesting capability for light energy-based Internet of Things (IoT) devices. PV modules facing multiple directions can lead to a situational energy loss when parts of the modules are shaded. To address this issue, existing solutions exploit reconfigurable PV arrays to acquire the optimal configuration in a given situation. However, conventional techniques are not energy efficient in estimating the harvesting capability of PV modules, and require high computation to find the optimal PV array at runtime. In this article, we propose PVoT, an energy-efficient reconfigurable PV array, which maximizes the harvesting energy for indoor IoT devices. To this end, we propose the use of photoresistors to estimate the harvesting capability with minimal energy overhead. We also provide hardware and software schemes, which perform event-driven light change detection in an energy-efficient way. Furthermore, we develop a power imbalance threshold metric to quickly find the optimal PV array at runtime. We implemented a prototype PVoT with off-the-shelf components and accompanying software. Experiments with the prototype hardware showed that PVoT achieves a gain of up to 23.9% in harvested energy compared to the existing directly connected PV array scheme.

关键词： Energy harvesting low-power system photovoltaic (PV) systems reconfigurable architectures shading effect

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