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作者： Niu, Xinyu Jin, Qiwei Luk, Wayne Weston, Stephen Imperial College London Department of Computing United Kingdom Maxeler Technologies London United Kingdom

Finite-difference methods are computationally intensive and required by many applications. Parameters of a finite-difference algorithm, such as grid size, can be varied to generate design space which contains algorithm instances with different constant coefficients. An algorithm instance with specific coefficients can either be mapped into general operators to construct static designs, or be implemented as constant-specific operators to form dynamic designs, which require runtime reconfiguration to update algorithm coefficients. This article proposes a tuning method to explore the design space to optimise both the static and the dynamic designs, and an evaluation method to select the design with maximum overall throughput, based on algorithm characteristics, design properties, available resources and runtime data size. For benchmark applications option pricing and Reverse-Time Migration (RTM), over 50% reduction in resource consumption has been achieved for both static designs and dynamic designs, while meeting precision requirements. For a single hardware implementation, the RTM design optimised with the proposed approach is expected to run 1.8 times faster than the best published design. The tuned static designs run thousands of times faster than the dynamic designs for algorithms with small data size, while the tuned dynamic designs achieve up to 5.9 times speedup over the corresponding static designs for large-scale finite-difference algorithms. © 2014 acm.

关键词： Finite difference method

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Heuristic search for adaptive, defect-tolerant multiprocessor arrays

Heuristic search for adaptive, defect-tolerant multiprocesso...

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transactions on Embedded Computing systems

作者： Vasilikos, Vasileios Smaragdos, Georgios Strydis, Christos Sourdis, Ioannis Delft University of Technology Netherlands Erasmus University Medical Center Netherlands Chalmers University of Technology Sweden

In this article, new heuristic-search methods and algorithms are presented for enabling highly efficient and adaptive, defect-tolerant multiprocessor arrays. We consider systems where a homogeneous multiprocessor array lies on top of reconfigurable interconnects which allow the pipeline stages of the processors to be connected in all possible configurations. Considering the multiprocessor array partitioned in substitutable units at the granularity of pipeline stages, we employ a variety of heuristic-search methods and algorithms to isolate and replace defective units. The proposed heuristics are designed for off-line execution and aim at minimizing the performance overhead necessarily introduced to the array by the interconnects' latency. An empirical evaluation of the designed algorithms is then carried out, in order to assess the targeted problem and the efficacy of our approach. Our findings indicate this to be a NP-complete computational problem, however, our heuristic-search methods can achieve, for the problem sizes we exhaustively searched, 100% accuracy in finding the optimal solution among 1019 possible candidates within 2.5 seconds. Alternatively, they can provide near-optimal solutions at an accuracy which consistently exceeds 70% (compared to the optimal solution) in only 10-4 seconds. © 2013 acm.

关键词： Heuristic methods Heuristic algorithms Modular robots Optimal systems Optimization Pipeline processing systems Pipelines Adaptable architecture Empirical evaluations Heuristic search methods Interconnection architecture Near optimal solutions Parallel processor Pipeline processor reconfigurable interconnects

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Solving the Global Atmospheric Equations through Heterogeneous reconfigurable Platforms

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acm transactions on reconfigurable technology and systems 2015年第2期8卷 1-16页

作者： Gan, Lin Fu, Haohuan Luk, Wayne Yang, Chao Xue, Wei Huang, Xiaomeng Zhang, Youhui Yang, Guangwen Tsinghua Univ Meng Minwei Sci Beijing 100084 Peoples R China Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2BZ England Chinese Acad Sci Inst Software Beijing 100190 Peoples R China Chinese Acad Sci State Key Lab Comp Sci Beijing 100190 Peoples R China Tsinghua Univ Beijing 100084 Peoples R China

One of the most essential and challenging components in climate modeling is the atmospheric model. To solve multiphysical atmospheric equations, developers have to face extremely complex stencil kernels that are costly in terms of both computing and memory resources. This article aims to accelerate the solution of global shallow water equations (SWEs), which is one of the most essential equation sets describing atmospheric dynamics. We first design a hybrid methodology that employs both the host CPU cores and the field-programmable gate array (FPGA) accelerators to work in parallel. Through a careful adjustment of the computational domains, we achieve a balanced resource utilization and a further improvement of the overall performance. By decomposing the resource-demanding SWE kernel, we manage to map the double-precision algorithm into three FPGAs. Moreover, by using fixed-point and reduced-precision floating point arithmetic, we manage to build a fully pipelined mixed-precision design on a single FPGA, which can perform 428 floating-point and 235 fixed-point operations per cycle. The mixed-precision design with four FPGAs running together can achieve a speedup of 20 over a fully optimized design on a CPU rack with two eight-core processors and is 8 times faster than the fully optimized Kepler GPU design. As for power efficiency, the mixed-precision design with four FPGAs is 10 times more power efficient than a Tianhe-1A supercomputer node.

关键词： Design Algorithms Performance Atmospheric equations high performance computing FPGAs hybrid algorithm mixed-precision design

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QUKU: A dual-layer reconfigurable architecture

QUKU: A dual-layer reconfigurable architecture

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作者： Bergmann, Neil W. Shukla, Sunil K. Becker, Jurgen School of ITEE University of Queensland st Lucia Brisbane 4072 Australia IBM TJ Watson Research Center Hawthorne NY 10532 United States ITIV Karlsruhe Institute of Technology 76131 Karlsruhe Germany

A new architecture, QUKU, is proposed for implementing stream-based algorithms on FPGAs, which combines the advantages of FPGA and Coarse Grain reconfigurable Arrays (CGRAs). QUKU consists of a dynamically reconfigurable, coarse-grain Processing Element (PE) array with an associated softcore processor providing system support. At a coarse-grain, the PE array can be reconfigured on a cycle-by-cycle basis to change the PE functionality similarly to that in a conventional CGRA. At a fine-grain, the whole FPGA can be reconfigured statically to implement a completely different PE array that serves the target application in a better way. Advantages of the fine-grain reconfiguration include individually customized PEs, adaptable numeric format support and customizable interconnect network. A prototype CAD tool framework is also developed which facilitates programming the QUKU architecture. An example application consisting of two different image detectors is implemented to demonstrate the advantages of QUKU. QUKU provides up to 140 times speedup and 40 times improvement in area-time product compared to an implementation running on an FPGA-based softcore. The area-time product for QUKU is around 16% lower than that of a custom circuit based implementation on the same FPGA. The per-PE customization provides an area-time saving of approximately 31% compared to a homogeneous 4 × 4 array of PEs for the same application. The experimental results demonstrate that a dual layered reconfigurable architecture provides significant potential benefits in terms of flexibility, area and processing efficiency over existing reconfigurable computing architectures for DSP. © 2013 acm.

关键词： Field programmable gate arrays (FPGA)

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Guest Editors' Introduction to Security in reconfigurable systems Design

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acm transactions on reconfigurable technology and systems 2009年第1期2卷 1-1页

作者： Schaumont, Patrick R. Jones, Alex K. Trimberger, Steve Univ Pittsburgh Pittsburgh PA 15260 USA Xilinx Inc San Jose CA 95124 USA Virginia Polytech Inst & State Univ Blacksburg VA 24061 USA

This special issue on Security in reconfigurable systems Design reports on recent research results in the design and implementation of trustworthy reconfigurable systems. Five articles cover topics including power-efficient implementation of public-key cryptography, side-channel analysis of electromagnetic radiation, side-channel resistant design, design of robust unclonable functions on an FPGA, and Trojan detection in an FPGA bitstream.

关键词： Security Reliability Design Trustworthy design side-channel resistant design physically unclonable function Trojan

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Rethinking Embedded Blocks for Machine Learning Applications

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acm transactions on reconfigurable technology and systems 2022年第1期15卷 1-30页

作者： Rasoulinezhad, Seyedramin Roorda, Esther Wilton, Steve Leong, Philip H. W. Boland, David Univ Sydney Sydney NSW 2006 Australia Univ British Columbia Vancouver BC V6T 1Z4 Canada

The underlying goal of FPGA architecture research is to devise flexible substrates that implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing, and image processing applications through high-precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: (1) higher computational density and (2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem formulation involving computing nested loops over multiply-accumulate (MAC) operations, which covers many basic linear algebra primitives and standard deep neural network (DNN) kernels. A quantitative methodology for deriving efficient coarse-grained compute block architectures from benchmarks is then proposed together with a family of new embedded blocks, called MLBlocks. An MLBlock instance includes several multiply-accumulate units connected via a flexible routing, where each configuration performs a few parallel dot-products in a systolic array fashion. This architecture is parameterized with support for different data movements, reuse, and precisions, utilizing a columnar arrangement that is compatible with existing FPGA architectures. On synthetic benchmarks, we demonstrate that for 8-bit arithmetic, MLBlocks offer 6x improved performance over the commercial Xilinx DSP48E2 architecture with smaller area and delay;and for timemultiplexed 16-bit arithmetic, achieves 2x higher performance per area with the same area and frequency. All source codes and data, along with documents to reproduce all the results in this article, are available at http://***/raminrasoulinezhad/MLBlocks.

关键词： FPGA Architectures coarse-grained compute blocks reconfigurable architecture neural networks digital signal processing

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FRL: Fast and reconfigurable Accelerator for Distributed Sound Source Localization

FRL: Fast and Reconfigurable Accelerator for Distributed Sou...

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acm/IEEE Int Conf on Hardware/Software Codesign and Syst Synthesis / Int Conf on Compilers, Architectures, and Synthesis for Embedded Syst / Int Conf on Embedded Software part of the Embedded Syst Week

作者： Ding, Xiaofeng Wang, Chengliang Liu, Heping Zhang, Zhihai Chen, Xianzhang Tan, Yujuan Liu, Duo Ren, Ao Chongqing Univ Coll Comp Sci Chongqing 400030 Peoples R China Chongqing Univ Coll Optoelect Engn Chongqing 400030 Peoples R China

Sound source localization (SSL) has been widely applied in industrial and civil fields. And with the development of wearable devices and the Internet of Things (IoT), it is attractive to deploy the SSL system onto embedded and portable devices. However, the software-based SSL system causes excessive response delay and is often affected by environmental noise. To overcome this obstacle, we propose the fast and precise localization (FPL) algorithm for distributed SSL systems. It combines the benefits of both time difference of arrival (TDOA) and steered response power (SRP) methods, and thus it is able to localize sound sources fast and precisely. To further improve the localization speed, we propose the fast and reconfigurable localization (FRL) accelerator, which is an algorithm-hardware co-designed SSL accelerator. It adopts multiple distributed localization nodes for higher localization precision and higher robustness to environmental interference, and it can be configured into either the fast or precise mode to adapt to various environments. Experimental evaluations show that our proposed FPL algorithm can achieve high localization speed and precision, and the field-programmable gate array (FPGA)-based FRL accelerator outperforms the software implementation by 48.6x and outperforms the prior FPGA-based SSL accelerators by 20x similar to 838.2x.

关键词： Field-programmable gate array (FPGA) reconfigurable architecture software-hardware co-design sound source localization (SSL)

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Test Compression for Dynamically reconfigurable Processors

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acm transactions on reconfigurable technology and systems 2011年第4期4卷 40-40页

作者： Inoue, Hiroaki Yamada, Junya Yoneda, Hideyuki Togawa, Katsumi Motomura, Masato Furuta, Koichiro NEC Corp Ltd Tokyo Japan Renesas Elect Santa Clara CA USA

We present the world's first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.

关键词： Design Dynamically reconfigurable processor double pattern compression

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Note from the TRETS EiC about the new Journal-first track in FPT'21

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acm transactions on reconfigurable technology and systems 2022年第1期15卷 1页

作者： Chen, Deming ACM Transact Reconfigurable Technol & Syst TRETS New York NY 10121 USA

No abstract available.

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A Retargetable Compilation Framework for Heterogeneous reconfigurable Computing

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acm transactions on reconfigurable technology and systems 2016年第4期9卷 24-24页

作者： Ul-Abdin, Zain Svensson, Bertil Halmstad Univ Sch Informat Technol CERES POB 823 SE-30118 Halmstad Sweden

The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable interconnection network. However, the mastering of low-level microarchitectural details involved in the programming of such massively parallel platforms becomes too cumbersome, which limits their adoption in many applications. Thus, there is a dire need for an approach to produce high-performance scalable implementations that harness the computational resources of the emerging reconfigurable platforms. This article addresses the grand challenge of accessibility of these diverse reconfigurable platforms by suggesting the use of a high-level language, occam-pi, and developing a complete design flow for building, compiling, and generating machine code for heterogeneous coarse-grained hardware. We have evaluated the approach by implementing complex industrial case studies and three common signal processing algorithms. The results of the implemented case studies suggest that the occam-pi language-based approach, because of its well-defined semantics for expressing concurrency and reconfigurability, simplifies the development of applications employing runtime reconfigurable devices. The associated compiler framework ensures portability as well as the performance benefits across heterogeneous platforms. CCS Concepts: . Computer systems organization -> reconfigurable computing;Heterogeneous (hybrid) systems;. Software and its engineering -> Retargetable compilers

关键词： reconfigurable processor arrays runtime reconfiguration compiler frameworks occam-pi

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