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TR-FSM: Transition-Based reconfigurable Finite State Machine

acm transactions on reconfigurable technology and systems 2011年第3期4卷 23-23页

作者： Glaser, Johann Damm, Markus Haase, Jan Grimm, Christoph Vienna Univ Technol Inst Comp Technol Vienna Austria

Finite State Machines (FSMs) are a key element of integrated circuits. Hard-coded FSMs do not allow changes after the ASIC production. While an embedded FPGA IP core provides flexibility, it is a complex circuit, requires difficult synthesis tools, and is expensive. This article presents and evaluates a novel architecture that is specifically optimized for implementing reconfigurable finite state machines: Transition-based reconfigurable FSM (TR-FSM). The architecture shows a considerable reduction in area, delay, and power consumption compared to FPGA architectures with a (nearly) FPGA-like reconfigurability.

关键词： Design Performance Theory reconfigurable logic finite state machine FPGA implementation low power wireless sensor network

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Design of Distributed reconfigurable Robotics systems with ReconROS

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acm transactions on reconfigurable technology and systems 2022年第3期15卷 27-27页

作者： Lienen, Christian Platzner, Marco Paderborn Univ Dept Comp Sci Comp Engn Grp Warburger Str 100 D-33098 Paderborn Germany

Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.

关键词： Robot operating sysstem (ROS) FPGA acceleration robotics

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A reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator

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acm transactions on reconfigurable technology and systems 2013年第4期6卷 17-17页

作者： Ananthan, T. Vaidyan, M. V. Natl Inst Technol Calicut Calicut 673601 Kerala India

The self-tuning regulator (STR) is a popular adaptive control algorithm. A high-performance computer is required for its implementation due to the heavy online computational burden. To extend STR for more real-time applications, a parallel hardware implementation on a low-cost reconfigurable computer is presented. The hardware was incorporated with multistage matrix multiplication (MMM) and trace technique to enhance the processing speed. This design was deeply pipelined to achieve high throughput. The algorithm was prototyped on a Xilinx field-programmable gate array (FPGA) device with a maximum operating frequency of 210.436 MHz. Application-specific integrated circuit (ASIC) implementation of STR was reported.

关键词： Algorithms Design Performance Adaptive control self-tuning regulator parallel hardware reconfigurable computer ASIC FPGA

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A Simulation Framework for Rapid Analysis of reconfigurable Computing systems

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acm transactions on reconfigurable technology and systems 2010年第4期3卷 25-25页

作者： Reardon, Casey Grobelny, Eric George, Alan D. Wang, Gongyu Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Gainesville FL 32611 USA

reconfigurable computing (RC) is rapidly emerging as a promising technology for the future of high-performance and embedded computing, enabling systems with the computational density and power of custom-logic hardware and the versatility of software-driven hardware in an optimal mix. Novel methods for rapid virtual prototyping, performance prediction, and evaluation are of critical importance in the engineering of complex reconfigurable systems and applications. These techniques can yield insightful tradeoff analyses while saving valuable time and resources for researchers and engineers alike. The research described herein provides a methodology for mapping arbitrary applications to targeted reconfigurable platforms in a simulation environment called RCSE. By splitting the process into two domains, the application and simulation domains, characterization of each element can occur independently and in parallel, leading to fast and accurate performance prediction results for large and complex systems. This article presents the design of a novel framework for system-level simulative performance prediction of RC systems and applications. The article also presents a set of case studies analyzing two applications, Hyperspectral Imaging (HSI) and Molecular Dynamics (MD), across three disparate RC platforms within the simulation framework. The validation results using each of these applications and systems show that our framework can quickly obtain performance prediction results with reasonable accuracy on a variety of platforms. Finally, a set of simulative case studies are presented to illustrate the various capabilities of the framework to quickly obtain a wide range of performance prediction results and power consumption estimates.

关键词： Performance Experimentation Verification reconfigurable computing discrete-event simulation performance prediction

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reconfigurable Architecture for VBSME with Variable Pixel Precision

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acm transactions on reconfigurable technology and systems 2012年第1期5卷 3-3页

作者： Olivares, Joaquin Univ Cordoba Dept Comp Architecture Elect & Elect Technol Cordoba 14001 Spain

Current video coding standards, e.g. MPEG-4 H.264/AVC, include Variable Block Size Motion Estimation, in this paper, this process is implemented by a reconfigurable architecture based on Signed Digit arithmetic. Bit serial computation is applied to reconfigure pixel precision. The reconfigurable architectural model is extremely simple to reconfigure. Pixel truncation is used to speed up computation saving up 23.5% of clock cycles for 4-bit precision. This design allows to process all motion vectors of a block in just one iteration. This system has been implemented in FPGA, and HDTVp results are presented. Main characteristics, of this architecture are: very reduced cost, high performance, and reconfigurable pixel precision, these features could be useful in mobile devices.

关键词： Design Performance FPGA architectures video coding variable block size motion estimation MPEG reconfigurable devices signed digit bit serial computation pixel truncation

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Titan-R: A Multigigabit reconfigurable Combined Compression/Decompression Unit

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acm transactions on reconfigurable technology and systems 2010年第2期3卷 7-7页

作者： Papadopoulos, Konstantinos Papaefstathiou, Ioannis Tech Univ Crete Dept Elect & Comp Engn ECED Khania Greece

Data compression techniques can alleviate bandwidth problems in even multigigabit networks and are especially useful when combined with encryption. This article demonstrates a reconfigurable hardware compressor/decompressor core, the Titan-R, which can compress/decompress data streams at 8.5 Gb/sec, making it the fastest reconfigurable such device ever proposed;the presented full-duplex implementation allows for fully symmetric compression and decompression rates at 8.5 Gbps each. Its compression algorithm is a variation of the most widely used and efficient such scheme, the Lempel-Ziv (LZ) algorithm that uses part of the previous input stream as the dictionary. In order to support this high network throughput, the Titan-R utilizes a very fine-grained pipeline and takes advantage of the high bandwidth provided by the distributed on-chip RAMs of state-of-the-art FPGAs.

关键词： Algorithms Design Performance Stream processing reconfigurable computing parallel processing hardware algorithms FPGA data compression networking

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SHMEM+: A Multilevel-PGAS Programming Model for reconfigurable Supercomputing

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acm transactions on reconfigurable technology and systems 2011年第3期4卷 26-26页

作者： Aggarwal, Vikas George, Alan D. Yoon, Changil Yalamanchili, Kishore Lam, Herman Univ Florida NSF Ctr High Performance Reconfigurable Comp CHRE Dept Elect & Comp Engn Gainesville FL 32611 USA

reconfigurable Computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such systems have demonstrated superior performance and reduced energy consumption versus their traditional counterparts based on microprocessors. However, most of such work has been limited to small system sizes. Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable HPC systems. In this article, we extend the traditional Partitioned Global Address Space (PGAS) model to provide a multilevel integration of memory, which simplifies development of parallel applications for such systems and improves developer productivity. The new multilevel-PGAS programming model captures the unique characteristics of reconfigurable HPC systems, such as the existence of multiple levels of memory hierarchy and heterogeneous computation resources. Based on this model, we extend and adapt the SHMEM communication library to become what we call SHMEM+, the first known SHMEM library enabling coordination between FPGAs and CPUs in a reconfigurable, heterogeneous HPC system. Applications designed with SHMEM+ yield improved developer productivity compared to current methods of multidevice RC design and exhibit a high degree of portability. In addition, our design of SHMEM+ library itself is portable and provides peak communication bandwidth comparable to vendor-proprietary versions of SHMEM. Application case studies are presented to illustrate the advantages of SHMEM+.

关键词： Design Languages Performance reconfigurable computing parallel programming programming language programming model productivity portability

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Floating-Point Exponentiation Units for reconfigurable Computing

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acm transactions on reconfigurable technology and systems 2013年第1期6卷 4-4页

作者： de Dinechin, Florent Echeverria, Pedro Lopez-Vallejo, Marisa Pasca, Bogdan Ecole Normale Super Lyon Lyon France Univ Politecn Madrid E-28040 Madrid Spain

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function x(y) as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

关键词： Design Algorithms Performance reconfigurable Computing floating-point power function exponentiation unit

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On the Evolution of Hardware Circuits via reconfigurable Architectures

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acm transactions on reconfigurable technology and systems 2012年第4期5卷 22-22页

作者： Cancare, Fabio Bartolini, Davide B. Carminati, Matteo Sciuto, Donatella Santambrogio, Marco D. Politecn Milan Milan Italy MIT Cambridge MA 02139 USA

Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed-the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature. FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

关键词： Design Algorithms Performance Experimentation reconfigurable hardware dynamic partial reconfiguration evolvable hardware evolutionary circuit design

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Hardware Decompression Techniques for FPGA-Based Embedded systems

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acm transactions on reconfigurable technology and systems 2009年第2期2卷 9-9页

作者： Koch, Dirk Beckhoff, Christian Teich, Juergen Univ Erlangen Nurnberg Erlangen Germany

In this work, we present hardware decompression accelerators for widening the bottleneck between slow nonvolatile memories on the one side and high-speed FPGA configuration interfaces and fast softcore CPUs on the other side. We discuss different compression algorithms suitable for a hardware accelerated decompression on FPGAs as well as on CPLDs. The algorithms will be investigated with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second under optimal conditions while only requiring slightly more than a hundred lookup tables. We will evaluate how these decompressors perform on configuration bitstreams for different FPGAs as well as for softcore CPU binaries.

关键词： Algorithms Experimentation Bitstream configuration reconfigurable computing

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