Traditional peer-to-peer (P2P) networks do not provide service differentiation and incentive for users. Consequently, users can obtain services without themselves contributing any information or service to a P2P commu...
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Traditional peer-to-peer (P2P) networks do not provide service differentiation and incentive for users. Consequently, users can obtain services without themselves contributing any information or service to a P2P community. This leads to the "free-riding" and "tragedy of the commons" problems, in which the majority of information requests are directed towards a small number of P2P nodes willing to share their resources. The objective of this work is to enable service differentiation in a P2P network based on the amount of services each node has provided to its community, thereby encouraging all network nodes to share resources. We first introduce a resource distribution mechanism between all information sharing nodes. The mechanism is driven by a distributed algorithm which has linear time complexity and guarantees Pareto-optimal resource allocation. Besides giving incentive, the mechanism distributes resources in a way that increases the aggregate utility of the whole network. Second, we model the whole resource request and distribution process as a competition game between the competing nodes. We show that this game has a Nash equilibrium and is collusion-proof. To realize the game, we propose a protocol in which all competing nodes interact with the information providing node to reach Nash equilibrium in a dynamic and efficient manner. Experimental results are reported to illustrate that the protocol achieves its service differentiation objective and can induce productive information sharing by rational network nodes. Finally, we show that our protocol can properly adapt to different node arrival and departure events, and to different forms of network congestion.
The proceedings contain 34 papers. The topics discussed include: a framework for modeling and optimization of prescient instruction prefetch;queueing systems with long-range dependent input process and subexponential ...
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ISBN:
(纸本)1581136641
The proceedings contain 34 papers. The topics discussed include: a framework for modeling and optimization of prescient instruction prefetch;queueing systems with long-range dependent input process and subexponential service times;modeling, simulation and measurements of queueing delay under long-tail Internet traffic;resilient multicast using overlays;run-time modeling and estimation of operating system power consumption;estimating membership in multicast session;dynamic resource allocation for shared data centers using online measurements;robustness of multicast congestion control to inflated subscription;an empirical evaluation of wide-area Internet bottlenecks;and spectroscopy of DNS update traffic.
There is a growing need for accurate power models at the system level. Memory structures such as caches, branch target buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the...
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ISBN:
(纸本)9781581139372
There is a growing need for accurate power models at the system level. Memory structures such as caches, branch target buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.
We present a novel domain analysis methodology that enables network researchers to quickly select the most accurate modeling and analysis method or methods for a given wired or wireless network path and network charac...
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ISBN:
(纸本)1581136641
We present a novel domain analysis methodology that enables network researchers to quickly select the most accurate modeling and analysis method or methods for a given wired or wireless network path and network characteristic of interest (e.g., delay, loss, or error process). Our approach includes two classical models, and two data preconditioning models developed in the Tapas project.
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