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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Ramakrishnan Rajamony Alan L. Cox Departments of Electrical & Computer Engineering Rice University Houston TX Departments of Electrical & Computer Science Rice University Houston TX

ISBN: (纸本)9780897919098

We describe a new approach to performance debugging that focuses on automatically identifying computation transformations to reduce synchronization and communication. By grouping writes together into equivalence classes, we are able to tractably collect information from long-running programs. Our performance debugger analyzes this information and suggests computation transformations in terms of the source code. We present the transformations suggested by the debugger on a suite of four applications. For Barnes-Hut and Shallow, implementing the debugger suggestions improved the performance by a factor of 1.32 and 34 times respectively on an 8-processor IBM SP2. For Ocean, our debugger identified excess synchronization that did not have a significant impact on performance. ILINK, a genetic linkage analysis program widely used by geneticists, is already well optimized. We use it only to demonstrate the feasibility of our approach to long-running *** also give details on how our approach can be implemented. We use novel techniques to convert control dependences to data dependences, and to compute the source operands of stores. We report on the impact of our instrumentation on the same application suite we use for performance debugging. The instrumentation slows down the execution by a factor of between 4 and 169 times. The log files produced during execution were all less than 2.5 Mbytes in size.

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Bounding of performance measures for a threshold-based queueing system with hysteresis 97

Bounding of performance measures for a threshold-based queue...

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Leana Golubchik John C. S. Lui Columbia University Department of Computer Science The Chinese University of Hong Kong Department of Computer Science & Engineering

ISBN: (纸本)9780897919098

In this paper, we consider a K-server threshold-based queueing system with hysteresis in which the number of servers, employed for servicing customers, is governed by a forward threshold vector F= (F1, F2, …, FK-1) (where F1 < F2 < … < FK-1) and a reverse threshold vector R= (R1, R2, …, RK-1) (where R1 < R2 < … < RK-1). There are many applications where a threshold-based queueing system can be of great use. The main motivation for using a threshold-based approach in such applications is that they incur significant server setup, usage, and removal costs. And, as in most practical situations, an important concern is not only the system performance but rather its cost/performance ratio. The motivation for use of hysteresis is to control the cost during momentary fluctuations in workload. An important and distinguishing characteristic of our work is that in our model we consider the time to add a server to be non-negligible. This is a more accurate model, for many applications, than previously considered in other works. Our main goal in this work is to develop an efficient method for computing the steady state probabilities of a multi-server threshold queueing system with hysteresis, which will, in turn, allow computation of various performance measures.

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Group-guaranteed channel capacity in multimedia storage servers

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Performance Evaluation Review 1997年第1期25卷 285-297页

作者： Tsiolis, Athanassios K. Vernon, Mary K. Univ of Wisconsin-Madison Madison United States

One of the open questions in the design of multimedia storage servers is in what order to serve incoming requests. Given the capability provided by the disk layout and scheduling algorithms to serve multiple streams simultaneously, improved request scheduling algorithms can reduce customer waiting times. This results in better service and/or lower customer loss. In this paper we define a new class of request scheduling algorithms, called Group-Guaranteed Server Capacity (GGSC), that preassign server channel capacity to groups of objects. We also define a particular formal method for computing the assigned capacities to achieve a given performance objective. We observe that the FCFS policy can provide the precise time of service to incoming customer requests. Under this assumption, we compare the performance of one of the new GGSC algorithms, GGSCW-FCFS, against FCFS and against two other recently proposed scheduling algorithms: Maximum Factored Queue length (MFQ), and the FCFS-n algorithm that preassigns capacity only to each of the n most popular objects. The algorithms are compared for both competitive market and captured audience environments. Key findings of the algorithm comparisons are that: (1) FCFS-n has no advantage over FCFS if FCFS gives time of service guarantees to arriving customers, (2) FCFS and GGSCW-FCFS are superior to MFQ for both competitive and captive audience environments, (3) for competitive servers that are configured for customer loss less than 10%, FCFS is superior to all other algorithms examined in this paper, and (4) for captive audience environments that have objects with variable playback length, GGSCW-FCFS is the most promising of the policies considered in this paper. The conclusions for FCFS-n and MFQ differ from previous work because we focus on competitive environments with customer loss under 10%, we assume FCFS can provide time of service guarantees to all arriving customers, and we consider the distribution of customer waiting

关键词： Interactive computer systems

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Queue management for explicit rate based congestion control

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Performance Evaluation Review 1997年第1期25卷 39-51页

作者： Ma, Qingming Ramakrishnan, K.K. Carnegie Mellon Univ Pittsburgh United States

Rate based congestion control has been considered desirable, both to deal with the high bandwidth-delay products of today's high speed networks, and to match the needs of emerging multimedia applications. Explicit rate control achieves low loss because sources transmit smoothly at a rate adjusted through feedback to be within the capacity of the resources in the network. However, large feedback delays, presence of higher priority traffic, and varying transient situations make it difficult to ensure feasibility (i.e., keep the aggregate arrival rate below the bottleneck resource's capacity) while also maintaining high resource utilization. These conditions along with the `fast start' desired by data applications often result in substantial queue buildups. We describe a scheme that manages the queue buildup at a switch even under the most aggressive patterns of sources, in the context of the Explicit Rate option for the Available Bit Rate (ABR) congestion control scheme. A switch observes the buildup of its queue, and uses it to reduce the portion of the link capacity allocated to sources bottlenecked at that link. We use the concept of a `virtual' queue, which tracks the amount of queue that has been `reduced', but has not yet taken effect at the switch. We take advantage of the natural timing of `resource management' (RM) cells transmitted by sources. The scheme is elegant in that it is simple, and we show that it reduces the queue buildup, in some cases, by more than two orders of magnitude and the queue size remains around a desired target. It maintains max-min fairness even when the queue is being drained. The scheme is scalable, and is as responsive as can be expected: within the constraints of the feedback delay. Finally, no changes are needed to the ATM Forum defined source/destination policies.

关键词： computer networks

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Managing server load in global memory systems 97

Managing server load in global memory systems

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Geoffrey M. Voelker Hervé A. Jamrozik Mary K. Vernon Henry M. Levy Edward D. Lazowska Department of Computer Science and Engineering University of Washington Department of Computer Science and Engineering University of Washington Seattle WA Computer Sciences Department University of Wisconsin-Madison

ISBN: (纸本)9780897919098

New high-speed switched networks have reduced the latency of network page transfers significantly below that of local disk. This trend has led to the development of systems that use network-wide memory, or global memory, as a cache for virtual memory pages or file blocks. A crucial issue in the implementation of these global memory systems is the selection of the target nodes to receive replaced pages. Current systems use various forms of an approximate global LRU algorithm for making these selections. However, using age information alone can lead to suboptimal performance in two ways. First, workload characteristics can lead to uneven distributions of old pages across servers, causing increased contention delays. Second, the global memory traffic imposed on a node can degrade the performance of local jobs on that *** paper studies the potential benefit and the potential harm of using load information, in addition to age information, in global memory replacement policies. Using an analytic queueing network model, we show the extent to which server load can degrade remote memory latency and how load balancing solves this problem. Load balancing requests can cause the system to deviate from the global LRU replacement policy, however. Using trace-driven simulation, we study the impact on application performance of deviating from the LRU replacement policy. We find that deviating from strict LRU, even significantly for some applications, does not affect application performance. Based upon these results, we conclude that global memory systems can gain substantial benefit from load balancing requests with little harm from suboptimal replacement decisions. Finally, we illustrate the use of the intuition gained from the model and simulation experiments by proposing a new family of algorithms that incorporate load considerations as well as age information in global memory replacement decisions.

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Design and evaluation of a DRAM-based shared memory ATM switch 97

Design and evaluation of a DRAM-based shared memory ATM swit...

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Tzi-cker Chiueh Srinidhi Varadarajan Computer Science Department State University of New York at Stony Brook Stony Brook NY

ISBN: (纸本)9780897919098

Beluga is a single-chip switch architecture specifically targeted at local area ATM networks, and it features three architectural innovations. First, an interconnection hierarchy composed of multiple switching fabrics is built into the chip to provide both low-latency cell transfer when the traffic is light and low cell drop rate under heavy load. Secondly, to improve silicon efficiency, Beluga is based on shared memory architecture, and the buffers are implemented using DRAM rather than SRAM technology. Heavy interleaving and selective invalidation are used to address long latency and periodic refreshing problems, respectively. Thirdly, Beluga supports multicast with minimal physical bit replication. It also separates support for unicast and multicast cells to optimize for the common case, where multicast cells occur infrequently. This paper describes the design details of Beluga and the results of a comprehensive simulation study to quantify the performance impact of each of its architectural features. The most important result from this research is that DRAM-based buffer implementation significantly reduces the cell-drop rate during heavy while exhibiting almost identical cell latency to SRAM-based implementation during light load. Therefore, we believe DRAM makes an attractive alternative for switch buffer implementation, especially for single-chip architecture such as Beluga.

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The utility of exploiting idle workstations for parallel computation 97

The utility of exploiting idle workstations for parallel com...

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Anurag Acharya Guy Edjlali Joel Saltz Department of Computer Science University of Maryland College Park

ISBN: (纸本)9780897919098

In this paper, we examine the utility of exploiting idle workstations for parallel computation. We attempt to answer the following questions. First, given a workstation pool, for what fraction of time can we expect to find a cluster of k workstations available? This provides an estimate of the opportunity for parallel computation. Second, how stable is a cluster of free machines and how does the stability vary with the size of the cluster? This indicates how frequently a parallel computation might have to stop for adapting to changes in processor availability. Third, what is the distribution of workstation idle-times? This information is useful for selecting workstations to place computation on. Fourth, how much benefit can a user expect? To state this in concrete terms, if I have a pool of size S, how big a parallel machine should I expect to get for free by harvesting idle machines. Finally, how much benefit can be achieved on a real machine and how hard does a parallel programmer have to work to make this happen? To answer the workstation-availability questions, we have analyzed 14-day traces from three workstation pools. To determine the equivalent parallel machine, we have simulated the execution of a group of well-known parallel programs on these workstation pools. To gain an understanding of the practical problems, we have developed the system support required for adaptive parallel programs and have used it to build an adaptive parallel computational fluid dynamics application.

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Cache behavior of network protocols 97

Cache behavior of network protocols

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Erich Nahum David Yates Jim Kurose Don Towsley Department of Computer Science University of Massachusetts Amherst MA

ISBN: (纸本)9780897919098

In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel running in user space on a MIPS R4400-based Silicon Graphics machine. We use the protocols to drive a validated execution-driven architectural simulator of our machine. We characterize the behavior of network protocol processing, deriving statistics such as cache miss rates and percentage of time spent waiting for memory. We also determine how sensitive protocol processing is to the architectural environment, varying factors such as cache size and associativity, and predict performance on future *** show that network protocol cache behavior varies widely, with miss rates ranging from 0 to 28 percent, depending on the scenario. We find instruction cache behavior has the greatest effect on protocol latency under most cases, and that cold cache behavior is very different from warm cache behavior. We demonstrate the upper bounds on performance that can be expected by improving memory behavior, and the impact of features such as associativity and larger cache sizes. In particular, we find that TCP is more sensitive to cache behavior than UDP, gaining larger benefits from improved associativity and bigger caches. We predict that network protocols will scale well with CPU speeds in the future.

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A performance evaluation of cluster architectures 97

A performance evaluation of cluster architectures

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Xiaohan Qin Jean-Loup Baer Department of Computer Science and Engineering University of Washington Seattle WA

ISBN: (纸本)9780897919098

This paper investigates the performance of shared-memory cluster-based architectures where each cluster is a shared-bus multiprocessor augmented with a protocol processor maintaining cache coherence across clusters. For a given number of processors, sixteen in this study, we evaluate the performance of various cluster configurations. We also consider the impact of adding a remote shared cache in each cluster. We use Mean Value Analysis to estimate the cache miss latencies of various types and the overall execution time. The service demands of shared resources are characterized in detail by examining the sub-requests issued in resolving cache misses. In addition to the architectural system parameters and the service demands on resources, the analytical model needs parameters pertinent to applications. The latter, in particular cache miss profiles, are obtained by trace-driven simulation of three *** results show that without remote caches the performance of cluster-based architectures is mixed. In some configurations, the negative effects of the longer latency of inter-cluster misses and of the contention on the protocol processor are too large to counter-balance the lower contention on the data buses. For two out of the three applications best results are obtained when the system has clusters of size 2 or 4. The cluster-based architectures with remote caches consistently outperform the single bus system for all 3 applications. We also exercise the model with parameters reflecting the current trend in technology making the processor relatively faster than the bus and memory. Under these new conditions, our results show a clear performance advantage for the cluster-based architectures, with or without remote caches, over single bus systems.

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Analyzing stability in wide-area network performance 97

Analyzing stability in wide-area network performance

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Proceedings of the 1997 acm SIGMETRICS international conference on measurement and modeling of computer systems

作者： Hari Balakrishnan Mark Stemm Srinivasan Seshan Randy H. Katz Computer Science Division University of California at Berkeley Berkeley CA IBM T.J. Watson Research Center Yorktown Heights NY

ISBN: (纸本)9780897919098

The Internet is a very large scale, complex, dynamical system that is hard to model and analyze. In this paper, we develop and analyze statistical models for the observed end-to-end network performance based on extensive packet-level traces (consisting of approximately 1.5 billion packets) collected from the primary Web site for the Atlanta Summer Olympic Games in 1996. We find that observed mean throughputs for these transfers measured over 60 million complete connections vary widely as a function of end-host location and time of day, confirming that the Internet is characterized by a large degree of heterogeneity. Despite this heterogeneity, we find (using best-fit linear regression techniques) that we can express the throughput for Web transfers to most hosts as a random variable with a log-normal distribution. Then, using observed throughput as the control parameter, we attempt to quantify the spatial (statistical similarity across neighboring hosts) and temporal (persistence over time) stability of network performance. We find that Internet hosts that are close to each other often have almost identically distributed probability distributions of throughput. We also find that throughputs to individual hosts often do not change appreciably for several minutes. Overall, these results indicate that there is promise in protocol mechanisms that cache and share network characteristics both within a single host and amongst nearby hosts.

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