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An analytic model of hierarchical mass storage systems with network-attached storage devices 96

An analytic model of hierarchical mass storage systems with ...

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Menascé, Daniel A. Pentakalos, Odysseas I. Yesha, Yelena Dept. Of Computer Science George Mason University FairfaxVA22030 United States Dept. Of C.S. And E.E. University Of Maryland Baltimore County BaltimoreMD21228 United States

ISBN: (纸本)0897917936

Network attached storage devices improve I/O performance by separating control and data paths and eliminating host intervention during data transfer. Devices are attached to a high speed network for data transfer and to a slower network for control messages. Hierarchical mass storage systems use disks to cache the most recently used files and tapes (robotic and manually mounted) to store the bulk of the files in the file system. This paper shows how queuing network models can be used to assess the performance of hierarchical mass storage systems that use network attached storage devices. The analytic model validated through simulation was used to analyze many different scenarios. © 1996 acm.

关键词： Data transfer

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Micro-architecture evaluation using performance vectors 96

Micro-architecture evaluation using performance vectors

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Krishnaswamy, Umesh Scherson, Isaac D. Dept. Of Information And Computer Science University Of California IrvineCA92717-3425 United States

ISBN: (纸本)0897917936

Benchmarking is a widely used approach to measure computer performance. Current use of benchmarks only provides running times to describe the performance of a tested system. Glancing through these execution times provides little or no information about system strengths and weaknesses. A novel benchmarking methodology is proposed to identify key performance parameters;the methodology is based on measuring performance vectors. A performance vector is a vector of ratings that represents delivered performance of primitive operations of a system. Measuring the performance vector of a system in a typical user workload can be a tough problem. We show how the performance vector falls out of an equation consisting of dynamic instruction counts and execution times of benchmarks. We present a non-linear approach for computing the performance vector. The efficacy of the methodology is ascertained by evaluating the micro-architecture of the Sun SuperSPARC superscalar processor using SPEC benchmarks. Results show interesting tradeoffs in the SuperSPARC and speak favorably of our methodology. © 1996 acm.

关键词： Benchmarking

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Bringing real-time scheduling theory and practice closer for multimedia computing 96

Bringing real-time scheduling theory and practice closer for...

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Gopalakrishnan, R. Parulkar, Gurudatta M. Department Of Computer Science Washington University St. Louis United States

ISBN: (纸本)0897917936

This paper seeks to bridge the gap between theory and practice of real-time scheduling in the domain of high speed multimedia networking. We show that the strict preemptive nature of real-time scheduling leads to more context switching, and requires system calls for concurrency control. We present our scheduling scheme called rate-monotonic with delayed preemption (rmdp) and show how it reduces both these overheads. We then develop the analytical framework to analyze rmdp and other scheduling schemes that lie in the region between strict (immediate) preemption and no preemption. Our idealized scheduler simulation methodology accounts for the blocking introduced by these schemes under the usual assumption that the time for context switching and preemption is zero. We derive simpler schedulability tests for non-preemptive scheduling, and prove a variant of rate-monotonic scheduling that has fewer preemptions. Our measurements on Sparc and Pentium platforms, show that for the workloads we considered, Rmdp increases useful utilization by as much as 8%. Thus our scheduling policies have the potential to improve performance over existing methods. © 1996 acm.

关键词： Concurrency control

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Crovella, Mark E. Bestavros, Azer Computer Science Department Boston University BostonMA02215 United States

ISBN: (纸本)0897917936

Recently the notion of self-similarity has been shown to apply to wide-area and local-area network traffic. In this paper we examine the mechanisms that give rise to the self-similarity of network traffic. We present a hypothesized explanation for the possible self-similarity of traffic by using a particular subset of wide area traffic: traffic due to the World Wide Web (WWW). Using an extensive set of traces of actual user executions of NCSA Mosaic, reflecting over half a million requests for WWW documents, we examine the dependence structure of WWW traffic. While our measurements are not conclusive, we show evidence that WWW traffic exhibits behavior that is consistent with self-similar traffic models. Then we show that the self-similarity in such traffic can be explained based on the underlying distributions of WWW document sizes, the effects of caching and user preference in file transfer, the effect of user "think time", and the superimposition of many such transfers in a local area network. To do this we rely on empirically measured distributions both from our traces and from data independently collected at over thirty WWW sites. © 1996 acm.

关键词： World Wide Web

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Web Server Workload Characterization: The Search for Invariants 96

Web Server Workload Characterization: The Search for Invaria...

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Arlitt, Martin F. Williamson, Carey L. Department Of Computer Science University Of Saskatchewan Canada

ISBN: (纸本)0897917936

The phenomenal growth in popularity of the World Wide Web (WWW, or the Web) has made WWW traffic the largest contributor to packet and byte traffic on the NSFNET backbone. This growth has triggered recent research aimed at reducing the volume of network traffic produced by Web clients and servers, by using caching, and reducing the latency for WWW users, by using improved protocols for Web *** to the goal of improving WWW performance is an understanding of WWW workloads. This paper presents a workload characterization study for Internet Web servers. Six different data sets are used in this study: three from academic (i.e., university) environments, two from scientific research organizations, and one from a commercial Internet provider. These data sets represent three different orders of magnitude in server activity, and two different orders of magnitude in time duration, ranging from one week of activity to one year of *** the study, emphasis is placed on finding workload invariants: observations that apply across all the data sets studied. Ten invariants are identified. These invariants are deemed important since they (potentially) represent universal truths for all Internet Web servers. The paper concludes with a discussion of caching and performance issues, using the invariants to suggest performance enhancements that seem most promising for Internet Web servers. © 1996 acm.

关键词： Web services

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Design and Analysis of Frame-based Fair Queueing: A New Traffic Scheduling Algorithm for Packet-Switched Networks 96

Design and Analysis of Frame-based Fair Queueing: A New Traf...

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Stiliadis, Dimitrios Varma, Anujan Computer Engineering Department University Of California Santa CruzCA95064 United States

ISBN: (纸本)0897917936

In this paper we introduce and analyze frame-based fair queueing, a novel traffic scheduling algorithm for packet-switched networks. The algorithm provides end-to-end delay bounds identical to those of PGPS (packet-level generalized processor sharing), without the complexity of simulating the fluid-model system in the background as required in PGPS. The algorithm is therefore ideally suited for implementation in packet switches supporting a large number of sessions. We present a simple implementation of the algorithm for a general packet switch. In addition, we prove that the algorithm is fair in the sense that sessions are not penalized for excess bandwidth they received while other sessions were idle. Frame-based fair queueing belongs to a general class of scheduling algorithms, which we call Rate-Proportional Servers. This class of algorithms provides the same end-to-end delay and burstiness bounds as PGPS, but allows more flexibility in the design and implementation of the algorithm. We provide a systematic analysis of this class of schedulers and obtain bounds on their fairness. © 1996 acm.

关键词： Scheduling algorithms

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Experiments with digital video playback 96

Experiments with digital video playback

引用

1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Gerber, Richard Gharai, Ladan Institute For Advanced Computer Studies Department Of Computer Science University Of Maryland College ParkMD20742 United States

ISBN: (纸本)0897917936

In this paper we describe our experiments on digital video applications, concentrating on the static and dynamic tradeoffs involved in video playback. Our results were extracted from a controlled series of 272 tests, which we ran in three *** the first stage of 120 tests, we used a simple player-monitor tool to evaluate the effects of various static parameters: compression type, frame size, digitized rate, spatial quality and keyframe distribution. The tests were carried out on two Apple Macintosh platforms: at the lower end a Quadra 950, and at the higher end, a Power PC 7100/80. Our quantitative metrics included average playback rate, as well as the rate's variance over one-second *** first set of experiments unveiled several anomalous latencies. To track them down we ran an additional 120 tests, from which we concluded that the video and IO operations were insufficiently tuned to each *** the next step we attempted to correct this problem, by implementing our own video playback software and accompanying device-level handlers. Our emphasis was on achieving a controlled, deterministic coordination between the various system components. An additional set of 32 experiments were carried out on our platforms, which showed frame-rate increases of up to 325%, with associated reductions in rate variance. © 1996 acm.

关键词： Quality control

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Integrating performance monitoring and communication in parallel computers 96

Integrating performance monitoring and communication in para...

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Martonosi, Margaret Ofelt, David Heinrich, Mark Dept. Of Electrical Engineering Princeton University United States Computer Systems Laboratory Stanford University United States

ISBN: (纸本)0897917936

A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers must increasingly be aware of the memory hierarchy as they implement software. Tools to support memory performance tuning have, however, been hobbled by the fact that it is difficult to observe the caching behavior of a running program. Little hardware support exists specifically for observing caching behavior;furthermore, what support does exist is often difficult to use for making fine-grained observations about program memory *** work observes that in a multiprocessor, the actions required for memory performance monitoring are similar to those required for enforcing cache coherence. In fact, we argue that on several machines, the coherence/communication system itself can be used as machine support for performance monitoring. We have demonstrated this idea by implementing the FlashPoint memory performance monitoring tool. FlashPoint is implemented as a special performance-monitoring coherence protocol for the Stanford FLASH Multiprocessor. By embedding performance monitoring into a cache-coherence scheme based on a programmable controller, we can gather detailed, per-data-structure, memory statistics with less than a 10% slowdown compared to unmonitored program executions. We present results on the accuracy of the data collected, and on how FlashPoint performance scales with the number of processors. © 1996 acm.

关键词： Cache memory

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Effective distributed scheduling of parallel workloads 96

Effective distributed scheduling of parallel workloads

引用

1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Dusseau, Andrea C. Arpaci, Remzi H. Culler, David E. Computer Science Division University Of California Berkeley United States

ISBN: (纸本)0897917936

We present a distributed algorithm for time-sharing parallel workloads that is competitive with coscheduling. Implicit scheduling allows each local scheduler in the system to make independent decisions that dynamically coordinate the scheduling of cooperating processes across processors. Of particular importance is the blocking algorithm which decides the action of a process waiting for a communication or synchronization event to complete. Through simulation of bulk-synchronous parallel applications, we find that a simple two-phase fixed-spin blocking algorithm performs well;a two-phase adaptive algorithm that gathers run-time data on barrier wait-times performs slightly better. Our results hold for a range of machine parameters and parallel program characteristics. These findings are in direct contrast to the literature that states explicit coscheduling is necessary for fine-grained programs. We show that the choice of the local scheduler is crucial, with a priority-based scheduler performing two to three times better than a round-robin scheduler. Overall, we find that the performance of implicit scheduling is near that of coscheduling (+/- 35%), without the requirement of explicit, global coordination. © 1996 acm.

关键词： Scheduling

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Embra: Fast and Flexible Machine Simulation 96

Embra: Fast and Flexible Machine Simulation

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1996 acm SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 1996

作者： Witchel, Emmett Rosenblum, Mendel Laboratory For Computer Science Massachusetts Institute Of Technology United States Computer Systems Laboratory Stanford University United States

ISBN: (纸本)0897917936

This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simulation environment, Embra models the processors of a MIPS R3000/R4000 machine faithfully enough to run a commercial operating system and arbitrary user applications. To achieve high simulation speed, Embra uses dynamic binary translation to generate code sequences which simulate the workload. It is the first machine simulator to use this technique. Embra can simulate real workloads such as multiprocess compiles and the SPEC92 benchmarks running on Silicon Graphic's IRIX 5.3 at speeds only 3 to 9 times slower than native execution of the workload, making Embra the fastest reported complete machine simulator. Dynamic binary translation also gives Embra the flexibility to dynamically control both the simulation statistics reported and the simulation model accuracy with low performance overheads. For example, Embra can customize its generated code to include a processor cache model which allows it to compute the cache misses and memory stall time of a workload. Customized code generation allows Embra to simulate a machine with caches at slowdowns of only a factor of 7 to 20. Most of the statistics generated at this speed match those produced by a slower reference simulator to within 1%. This paper describes the techniques used by Embra to achieve high performance, focusing on the requirements unique to machine simulation, including modeling the processor, memory management unit, and caches. In order to study Embra's memory system performance we use the SimOS simulation system to examine Embra itself. We present a detailed breakdown of Embra's memory system performance for two cache hierarchies to understand Embra's current performance and to show that Embra's implementation techniques benefit significantly from the larger cache hierarchies that are becoming available. Embra has been used for ope

关键词： Simulators

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