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检索条件"任意字段=Advanced Etch Technology and Process Integration for Nanopatterning XII 2023"

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advanced etch technology and process integration for nanopatterning xii

Advanced Etch Technology and Process Integration for Nanopat...

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advanced etch technology and process integration for nanopatterning xii 2023

ISBN: (纸本)9781510661059

The proceedings contain 22 papers. The topics discussed include: evaluation of TiN hardmask films to prevent line wiggling due to plasma-induced film stress;process optimization for shallow trench isolation etch using computational models;high-aspect-ratio amorphous carbon mask etch profile control through plasma and surface chemistry optimization;a method for achieving sub-2nm across-wafer uniformity performance;computational patterning and process variation impact on photonics devices;variability study of MP18 semi-damascene interconnects with fully self-aligned vias;a novel approach to etch-process-aware intensive layout retarget;selective isotropic atomic-layer etching of thin films by using dry chemical removal tool;selective isotropic atomic-layer etching of thin films by using dry chemical removal tool;and the damage control of sub layer while ion-driven etching with vertical carbon profile implemented.

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Advances in low GWP etch gasses 12

Advances in low GWP etch gasses

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Jennings, Colin Nguyen, Phong Biltek, Scott Stafford, Nathan Innovation Campus Delaware Air Liquide 200 GBC Dr NewarkDE19702 United States

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

Fluorinated species are ubiquitous in semiconductor manufacturing, yet are known to have global warming potentials thousands of times higher than CO2. As abatement technologies are not completely effective and add additional costs, interest in reducing these emissions increases with semiconductor manufacturing volumes. We explore alternative chemistries for common plasma etch applications that retain patterning performance but with near zero GWP. Spectroscopic identification and quantification of etch byproducts is presented to demonstrate the beneficial environmental impacts of transitioning from the most common etch gasses. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Environmental impact

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Radical-based surface treatment and selective etch enabled by high density ICP remote plasma source 12

Radical-based surface treatment and selective etch enabled b...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Zhang, Qi Yang, Haichun Hsieh, Yueh-Ling Chen, Jiajun Yang, Jiaying Xie, Ting Wang, Shanyu Chung, Hua Mattson Technology Inc. FremontCA94538 United States

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

With Moore's law continues to drive IC feature size and device density, advanced technology evolves to enable not only smaller feature size but also 3D structures for logic and memory chipmakers.1 The associated process requires precise surface/interface functionality and material loss control, as a result plasma damage free process and isotropic etch with high selectivity became crucial for advanced 3D transistor manufacturing. High density radical based processes provide ideal solutions with very low electron temperature, excellent step coverage and ultra-high selectivity. The highly reactive radicals can largely reduce thermal budget as well. In this article radical based surface treatments and material modifications including metal treatment, surface reduction and surface smoothing are discussed. Furthermore, the benefits of combining such surface treatment and radical based selective etch are also presented with examples of Si and TiN etch processes. Both surface treatment and selective etch processes are enabled by high density ICP plasmas generated radicals. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Budget control

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Opportunities and challenges of heterogeneous integration: from IC packaging POV 12

Opportunities and challenges of heterogeneous integration: f...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Chiang, Jeffery Wu, Paul Hsinchu Science Park Branch Powertech Technology Inc. No. 15 Lixing 3rd Rd. Hsinchu Science Park Hsinchu City30078 Taiwan

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

The IC assembly industry has gone a full circle over the course of 50 years. At the beginning, everything was discretely packaged, but with the introduction of integrated circuits and advancement of lithograph y technologies, we were able to keep putting more into less., Yet the industry is facing challenges in continuing the scaling trend without sacrificing th e economic gain, therefore they turned to the heterogeneous integration, where the different IP blocks on the SOC were, once again, split into several discrete IC chips, thereby completing the circle. How do we enable these physically separated chips to have a performance that is on par with a single SOC? The answer is advanced packaging. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Timing circuits

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Enabling process technologies for advanced logic devices beyond FinFET era 12

Enabling process technologies for advanced logic devices bey...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Yamamoto, Tomonari Tokyo Electron Ltd. 3-1 Akasaka 5-chome Minato-ku Tokyo107-6325 Japan

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Computer circuits

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Sustainable semiconductor manufacturing: lessons for lithography and etch 12

Sustainable semiconductor manufacturing: lessons for lithogr...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Gallagher, Emily Bezard, Philippe Boakes, Lizzie Firrincieli, Andrea Rolin, Cedric Ragnarsson, Lars-Åke Imec Vzw Kapeldreef 75 Leuven Belgium

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

Sustainability is gaining momentum as countries and companies announce targets for net-zero carbon emissions by 2050. imec has created a bottom-up model using tool data, process recipes, and integrated wafer process flows to create a virtual fab. With this model, it is possible to quantify the environmental impact of manufacturing integrated circuit (IC) chips for current and future logic and memory technology modes. In this paper, the model is used to identify areas with the highest environmental impact. It is important to reduce the impact of both lithography and etch since together they are responsible for 45% of total CO2 equivalent emissions associated with fabricating an N3 logic node wafer. For lithography, two approaches to reducing the environmental impact will be described: one concentrates on tool consumption and the other on process choices to maximize throughput. For etch, the focus is on reducing overall gas consumption and improving wafer material stacks to minimize fluorocarbon use. Translating patterning process changes into emission numbers will enable informed process choices for future and contribute to a shift towards net-zero semiconductor manufacturing. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Environmental impact

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process optimization for shallow trench isolation etch using computational models 12

Process optimization for shallow trench isolation etch using...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Huang, Shuo Panneerchelvam, Prem Huard, Chad M. Sridhar, Shyam Ventzek, Peter L. G. Smith, Mark D. Kla Corporation 1200 Woodridge Ave Ann ArborMI48105 United States Kla Corporation 8834 N. Capital of Texas HW Suite 301 AustinTX78759 United States Tokyo Electron America Inc. 2400 Grove Blvd. AustinTX78741 United States Kla Corporation 1 Technology Drive MilpitasCA95035 United States

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

In today's advanced semiconductor process manufacturing, critical dimensions of device features have decreased to a few nanometers while the aspect ratios have increased beyond 100. The cost of process development has significantly increased and the performance of the lithography and plasma etch patterning processes are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a three-dimensional Monte Carlo-based feature scale model, Proetch®, has been developed for modeling etch process with the capability of optimizing the process by solving forward and inverse problems. The shallow trench isolation etch process in self-aligned double patterning was investigated. The mechanism of silicon etch by Ar/Cl2 plasma was developed with experimental data as a reference. The developed model captures the trends and has quantitative accuracy in comparison to the experimental data, and can be used to identify the different fundamental pathways which contribute to the profile metrics. The developed model was then used to solve the forward problem, which is to predict profiles at different process conditions, and the inverse problem, which is to search for the process conditions (e.g, power and pressure) which could result in desirable profiles. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Optimization

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A novel approach to etch-process-aware intensive layout retarget 12

A novel approach to etch-process-aware intensive layout reta...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Lee, Jeeyong Heo, Yangwoo Lee, Ryanggeun Kim, Sangwook Hong, Jisuk Koo, Kyoil Yim, Changmook Kim, Jungmin Lee, Sooyong Kim, Joonsung Kim, Dongho Yang, Seung-Hune Jeong, Seongtae Samsung Electronics Co. Ltd. Samsung Jeonja-ro #1 Hwasung18448 Korea Republic of

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

Patterning, a major process in semiconductor manufacturing, aims to transfer the design layout to the wafer. Accordingly, the "process proximity correction"method was developed to overcome the difference in after-cleaninginspected CD (critical dimension) between patterns of similar shapes. However, its physical model is often limited in the predictive performance. Therefore, recent studies have introduced ML (machine learning) technology to supplement model accuracy, but this approach often has an inherent risk of overfitting depending on the type of sampled pattern. In this study, we present a newly invented flow capable of stable etch-process-aware ML modeling by model reconstruction and large amounts of measurement data. The new modeling flow can also be performed within a reasonable runtime through efficient feature extraction. Based on the new model and its related layout targeting platform, intensive improvements were made to CD targeting and spread;for a given layout, in comparison with delicate rule-based modification, the CD targeting accuracy was improved by 4 times and approaches the limit of metrology error. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Machine learning

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The impact of electron temperature on etch profiles in Ar/CF4 plasmas 14

The impact of electron temperature on etch profiles in Ar/CF...

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advanced etch technology and process integration for nanopatterning XIV

作者： Kim, Nayeon Park, Junyoung Choi, Jung-Eun Kim, Min-Seok Lee, MyeongJae Chung, Chin-Wook Department of Electrical Engineering Hanyang University Seoul04763 Korea Republic of Department of Physics Hanyang University Seoul04763 Korea Republic of

ISBN: (纸本)9781510686441

As high aspect ratio etching becomes increasingly essential in semiconductor manufacturing, vertical etching has gained significant importance. This study investigates the reduction of undercut in silicon (Si) patterned with a high aspect ratio SiO2 mask, utilizing ultra-low electron temperature (ULET) plasma. A vertical etch profile devoid of undercut is achieved in the ULET plasma (Te = 0.3 eV). This ULET plasma is generated through an inductively coupled plasma with a DC-biased grid. As the electron temperature decreases with increasing grid voltage, the lateral etch rate diminishes, resulting in a more vertical profile. Conversely, an increase in RF bias power leads to the observation of undercut and bowing in the etch profile due to a rise in electron temperature associated with the RF bias power. These findings demonstrate that the electron temperature, which influences the etch species, is a critical factor governing the etch profile. Consequently, this ULET plasma presents a viable approach for etching silicon at the atomic scale. © 2025 SPIE.

关键词： Semiconductor plasmas

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Understanding etch properties of advanced chemically amplified EUV resist 12

Understanding etch properties of advanced chemically amplifi...

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advanced etch technology and process integration for nanopatterning xii 2023

作者： Park, Jong Keun Aqad, Emad Cen, Yinjie Coley, Suzanne M. Cui, Li Hoelzel, Conner Naab, Benjamin D. Lee, Choongbong Rena, Rochelle Kang, Philjae Shin, You Rim Limberg, David Zhang, Lei DuPont Electronics and Industrial 455 Forest Street MarlboroughMA01752 United States DuPont Electronics and Industrial 20 Samsung 1-Ro 5-Gil Hwaseong Gyeonggi-Do18449 Korea Republic of DuPont Science and Innovation 200 Powder Mill Road WilmingtonDE19803 United States

ISBN: (数字)9781510661066

ISBN: (纸本)9781510661059

Extreme ultraviolet (EUV) lithography technology empowers integrated circuit industry to mass produce chips with smaller pitches and higher density. Along with EUV tool advancement, significant progress has also been made in the development and advancement of EUV chemically amplified resist (CAR) materials, which allows for the improvement of resolution, line edge roughness, and sensitivity (RLS) trade-off. The scarce number of EUV photons has triggered the development of resist material with high absorption at 13.5 nm. However, a review of open literature reveals very limited reports on the effect of high EUV absorption elements on etch properties of advanced EUV resist. To ensure Moore's Law continues to move forward, further resist performance improvement is required. In this regard, stochastic defects originating from photon shot noise, materials, and processing variabilities present a unique challenge for the extension of CAR platform for the patterning of smaller nodes. Notably, less attention has been paid to defects formed during the etching process used for pattern transfer. In this paper, we report on the relationship between resist make-up and etch properties. In particular, the effect of incorporation of EUV high absorbing elements are examined. New resist material design strategies for continuous improvement of EUV CAR lithographic performance will be discussed. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Photoresists

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