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Conference on advanced signal processing algorithms, architectures, and implementations XvI

作者： Barnard, R. Pauca, v. P. Torgersen, T. C. Plemmons, R. J. Prasad, S. van der Gracht, J. Nagy, J. Chung, J. Behrmann, G. Mathews, S. Mirotznik, M. Wake Forest Univ Dept Comp Sci Winston Salem NC 27109 USA Emory Univ Dept Math & Comp Sci Atlanta GA 30322 USA Wake Forest Univ Dept Math Winston Salem NC 27109 USA Holospex Inc Columbia MD 21044 USA EM Photon Inc Newark DE 19711 USA Catholic Univ Amer Dept Elect Engn & Comp Sci Washington DC 20064 USA Univ New Mexico Ctr Adv Studies Albuquerque NM 87131 USA Univ New Mexico Dept Phys & Astron Albuquerque NM 87131 USA

ISBN: (纸本)0819463922

We investigate the use of a novel multi-lens imaging system in the context of biometric identification, and more specifically, for iris recognition. Multi-lenslet cameras offer a number of significant advantages over standard single-lens camera systems, including thin form-factor and wide angle of view. By using appropriate lenslet spacing relative to the detector pixel pitch, the resulting ensemble of images implicitly contains subject information at higher spatial frequencies than those present in a single image. Additionally, a multi-lenslet approach enables the use of observational diversity, including phase, polarization, neutral density, and wavelength diversities. For example, post-processing multiple observations taken with differing neutral density filters yields an image having an extended dynamic range. Our research group has developed several multi-lens camera prototypes for the investigation of such diversities. In this paper, we present techniques for computing a high-resolution reconstructed image from an ensemble of low-resolution images containing sub-pixel level displacements. The quality of a reconstructed image is measured by computing the Hamming distance between the Daugman(4) iris code of a conventional reference iris image, and the iris code of a corresponding reconstructed image. We present numerical results concerning the effect of noise and defocus blur in the reconstruction process using simulated data and report preliminary work on the reconstruction of actual iris data obtained with our camera prototypes.

关键词： Cameras Iris recognition Image resolution Sensors Image registration Image quality Charge-coupled devices Imaging systems Prototyping Point spread functions

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Programmable processor design for Givens rotations based applications

Programmable processor design for Givens rotations based app...

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4th IEEE Sensor Array and Multichannel signal processing Workshop

作者： Dickson, K. Liu, Z. McCanny, J. v. Queens Univ Belfast Inst Elect Commun & Informat Technol Belfast BT3 9DT Antrim North Ireland

ISBN: (纸本)1424403081

A wide range of applications involve matrix decompositions which can be computed using Givens rotations. A programmable processor for Givens rotations offers more flexibility than highly tailored systolic array hardware implementations. The programmable processor design presented in this paper employs an approximate rotations method to compute Givens rotations. Instantiations of this programmable processor can then be arranged/configured (i.e. in arrays of varying size and dimension) according to the requirements of the target application. Another advantage of this approach is that the processor can be programmed to compute different algorithms (e.g. QR decomposition, singular-value decomposition or a combination of both).

关键词： Program processors

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High throughput, low cost, fully pipelined architecture for AES crypto chip

High throughput, low cost, fully pipelined architecture for ...

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2006 Annual India Conference, INDICON

作者： Iyer, Nalini C. Anandmohan, P.v. Poornaiah, D.v. Kulkarni, v.D. IEEE Dept. of E and C BVBCET Hubli India ECIL Bangalore India ITI Bangalore India CG-Coreel Bangalore India

ISBN: (纸本)1424403707

Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms. Several papers described efficient architectures for ASICs and FPGAs. various approaches for efficient hardware implementation of the advanced Encryption Standard algorithm based on architectural optimization and algorithmic optimizationfor different modes are discussed and implemented. This paper proposes Compact, Memory less, high-speed hardware architectures for the Rijndael AES Encryptor/Decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and subpipelining. Speed is Increased by processing multiple rounds simultaneously at the cost of increased area. Algorithmic optimization exploits algorithmic strength inside each round unit. various methods such as Resource sharing and Common sub expression elimination method for realizing various transformations in each round unit are presented to reduce the critical path and area issues between encryptor and decryptor. advantage of sub-pipelining can be further explored by eliminating the unbreakable delay incurred by look-up tables in the conventional approaches, the widely used implementation of S-box, which uses combinational logic only. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic such as multiplication and inversion.. Our technique involves mapping field elements to a composite field representation and a representation technique which minimizes the computation cost of the relevant arithmetic. Our method results in a very compact and fast gate circuit for Rijndael encryption and decryption The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle The performance results for various architectural designs su

关键词： Throughput

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Conjugate Distributed Arithmetic Adaptive FIR Filters and their Hardware Implementation

Conjugate Distributed Arithmetic Adaptive FIR Filters and th...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Walter Huang venkatesh Krishnan David v. Anderson Center for Signal and Image Processing School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

Adaptive filtering constitutes an important class of DSP algorithms employed in several hand held mobile devices for applications such as echo cancellation, signal de-noising, and channel equalization. In this paper, a new hardware architecture using conjugate distributed arithmetic (CDA) which is suitable for high throughput hardware implementations of LMS adaptive filters is presented. Unlike a traditional distributed arithmetic (DA) implementation where all possible combination sums of the filter coefficients are stored in a look-up-table (LUT), in the CDA architecture, all possible combination sums of the input signal samples are stored in the LUT and updated at the arrival of every sample using an efficient update procedure. We describe the design of CDA adaptive filters and show that practical implementations of CDA adaptive filters have very high throughput relative to multiply and accumulate architectures. We also show that CDA adaptive filters have a potential area and power consumption advantage over DSP microprocessor architectures for a given throughput.

关键词： Arithmetic Finite impulse response filter Hardware Adaptive filters Throughput Digital signal processing Table lookup Filtering algorithms Echo cancellers signal denoising

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advanced receiver algorithms for MIMO wireless communications 06

Advanced receiver algorithms for MIMO wireless communication...

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Design, Automation and Test in Europe Conference and Exhibition

作者： A. Burg M. Borgmanr M. Wenk C. Studer H. Bolcskei Integrated Systems Laboratory ETH Zurich Zurich Switzerland Communication Technology Laboratory ETH Zurich Zurich Switzerland

ISBN: (纸本)9783981080100

We describe the vLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area. In particular, algorithms and vLSI architectures for sphere decoding (SD) and K-best detection are considered, and the corresponding trade-offs between uncoded error-rate performance, silicon area, and throughput are explored. We show that SD with a per-block run-time constraint is best suited for practical implementations

关键词： MIMO Wireless communication signal processing algorithms Detectors Throughput very large scale integration Silicon Receiving antennas Laboratories Maximum likelihood decoding

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Proceedings of SPIE: advanced signal processing algorithms, architectures, and implementations Xv

Proceedings of SPIE: Advanced Signal Processing Algorithms, ...

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advanced signal processing algorithms, architectures, and implementations Xv

The proceedings contain 36 papers. The topics discussed include: optimal and suboptimal detection of Gaussian signals in noise: asymptotic relative efficiency;some effects of mutual coupling and noise on channel capacity between antenna arrays;an optimum MIMO signaling for antenna selection and interference;adaptive cluster selection for collaborative beamforming in ground sensors communications with UAv;regression in sensor networks: training distributively with alternating projections;improved orthogonal frequency division multiplexing communications through advanced coding;and MP3 compression and transmission of infrasonic sensor array signals and task-specific matrics for distortion evaluation.

关键词： Spurious signal noise

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Computationally efficient systolic architecture for computing the discrete Fourier transform

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IEEE TRANSACTIONS ON signal processing 2005年第12期53卷 4640-4651页

作者： Nash, JG Centar Los Angeles CA 90077 USA

A new high-performance systolic architecture for calculating the discrete Fourier transform (DFT) is described which is based on two levels of transform factorization. One level uses an index remapping that converts the direct transform into structured sets of arithmetically simple four-point transforms. Another level adds a row/column decomposition of the DFT. The architecture supports transform lengths that are not powers of two or based on products of coprime numbers. Compared to previous systolic implementations, the architecture is computationally more efficient and uses less hardware. It provides low latency as well as high throughput, and can do both one- and two-dimensional DFTs. An automated computer-aided design tool was used to find latency and throughput optimal designs that matched the target field programmable gate array structure and functionality.

关键词： computation fast algorithms parallel processing architectures systolic and wavefront architectures transforms

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Equivalence of Hadamard matrices and pseudo-noise matrices

Equivalence of Hadamard matrices and pseudo-noise matrices

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advanced signal processing algorithms, architectures, and implementations Xv

作者： Bella, T. Olshevsky, v. Sakhnovich, L. Department of Mathematics University of Connecticut Storrs CT 06269-3009 United States

Several classes of structured matrices (e.g., the Hadamard-Sylvester matrices and the pseudo-noise matrices) are used in the design of error-correcting codes. In particular, the columns of matrices belonging to the above two matrix classes are often used as codewords. In this paper we show that the two above classes essentially coincide: the pseudo-noise matrices can be obtained from the Hadamard-Sylvester matrices by means of the row/column permutations.

关键词： Matrix algebra

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FPGA-based high-performance arithmetic pipeline synthesis for DSP applications

FPGA-based high-performance arithmetic pipeline synthesis fo...

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advanced signal processing algorithms, architectures, and implementations Xv

作者： Liddicoat, Albert A. Cary, Shawn Pang, Jackson Department of Electrical Engineering California Polytechnic State University San Luis Obispo

Today FPGAs are used in many digital signal processing applications. In order to design high-performance area efficient DSP pipelines various arithmetic functions and algorithms must be used. In this work, FPGA-based functional units for Cosine, Arctangent, and the Square Root functions are designed using bipartite tables and iterative algorithms. The bipartite tabular approach was four to 12 times faster than the iterative approach but requires 8-40 times more FPGA hardware resources to implement these functions. Next, these functions along with the FPGA hardware multipliers and a reciprocal bipartite table unit are used for hardware rectangular-to-polar and polar-to-rectangular conversion macro-functions. These macro-functions allow for a 7-10 times performance improvement for the high-performance pipelines or an area reduction of 9-17 times for the low cost implementations. In addition, software tool to design FPGA based DSP pipelines using the Cosine, Sine, Arctangent, Square Root, and Reciprocal units with the hardware multipliers is presented.

关键词： Digital signal processing

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A higher order method for concentrating the STFT

A higher order method for concentrating the STFT

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advanced signal processing algorithms, architectures, and implementations Xv

作者： Nelson, D.J. Smith, D.C. R61 U.S. Dept. of Defense Ft. Meade MD 20755 United States

We present a method for computing the theoretically exact estimate of the instantaneous frequency of a signal from local values of its short time Fourier transform under the assumption that the complex logarithm of the signal is a polynomial in time. We apply the method to the problem of estimating and separating non-stationary components of a multi-component signal. signal estimation and separation is based on a linear TF model in which the value of the signal at each time is distributed in frequency. This is a significant departure from the conventional nonlinear model in which signal energy is distributed in time and frequency. We further demonstrate by a simple example that IF estimated by the higher order method is significantly better than previously used first order methods.

关键词： signal processing

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