A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SH...
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A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SHARC DSPs), with a variety of parallel DSP array architectures possible. The network fabric is intended to be reconfigurable (within a rich but necessarily limited set of structures) to adapt to the needs of a sequence of image processingalgorithms being executed (e.g., in a medical image processing environment). The testbed will exploit conventional FPGA components to provide reconfigurable network structures and will exploit commercial high-speed interconnect components emerging for applications such as board-to-board applications. As a computational accelerator, the testbed is intended to be controlled by a host processor, with the host processor cooperating in the definition of the changes in the structure of the network structure as execution of a sequence of image processingalgorithms proceeds.
The proceedings contain 41 papers. The topics discussed include: vLSI digital signalprocessing: some arithmetic issues;near canonic double-based number system (DBNS) with applications in digital signalprocessing;nov...
The proceedings contain 41 papers. The topics discussed include: vLSI digital signalprocessing: some arithmetic issues;near canonic double-based number system (DBNS) with applications in digital signalprocessing;novel high-speed bit-parallel multiply accumulate arithmetic architecture;low-power radix 2 division algorithm with minimum add/sub operations;DSP implementation of source location using microphone arrays;one-sided algorithm for subspace projection beam-forming;modern microphone array for hearing aid and speech processing;signalprocessingalgorithms by permutation test in radar application;and time-sequenced adaptive filtering using a modified P-vector algorithm.
The topics discussed are cumulants;time frequency signal analysis;mobile communications;nonlinear dynamics and signalprocessing;subspace tracking;array processing;fast solvers for structured systems;regularization me...
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ISBN:
(纸本)0819416207
The topics discussed are cumulants;time frequency signal analysis;mobile communications;nonlinear dynamics and signalprocessing;subspace tracking;array processing;fast solvers for structured systems;regularization methods;frequency representations and machine implementations;architectures;and algorithm based fault tolerance.
In this paper, we introduce modifications on the classic CORDIC algorithm to reduce the number of iterations, and hence the rounding noise. The modified algorithm needs, at most, half the number of iterations to achie...
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A methodology for constructing parallel embedded DSP systems is described. The method uses a software and embedded processor abstraction to help raise the level of problem analysis above the raw state machine concept....
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作者:
Rohrbaugh, RUSN
CTR SURFACE WARFAREADV SIGNAL PROC BRANCHBREMERTONWA 98314
Time-frequency methods are applied for bearing analysis of a motor-generator. We show that these methods reveal features that are not seen by traditional methods, such as the power spectrum. These features may be used...
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ISBN:
(纸本)0819422347
Time-frequency methods are applied for bearing analysis of a motor-generator. We show that these methods reveal features that are not seen by traditional methods, such as the power spectrum. These features may be used for detection of specific faults and as supplemental information to assess the condition of the machine.
In this paper we explore a new number system which uses a double base. The representation of the numbers has a very simple geometric interpretation, allowing potentially fast implementation of the basic arithmetic ope...
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In this review paper we discuss selected issues associated with the implementation of arithmetic for vLSI Digital signal Processors. We start with a Silicon Technology Roadmap view of the next decade, in order to gras...
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ISBN:
(纸本)0819422347
In this review paper we discuss selected issues associated with the implementation of arithmetic for vLSI Digital signal Processors. We start with a Silicon Technology Roadmap view of the next decade, in order to grasp some of the issues facing the next generation of vLSI designers, particularly associated with high performance DSP systems. We use this roadmap to open the discussion on the role basic arithmetic operations play in the construction of DSP systems; in particular we look at the interplay between algorithms, architecture, arithmetic representation and circuit implementation. Many of the illustrative examples are taken from work conducted in the vLSI Research Group, University of Windsor over the past few years, including on- going work.
This paper considers a class of blind beamforming problems in which the amount of prior information is very limited. The array sensors are placed in unknown locations within a geographical region, and have unknown fre...
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ISBN:
(纸本)0819422347
This paper considers a class of blind beamforming problems in which the amount of prior information is very limited. The array sensors are placed in unknown locations within a geographical region, and have unknown frequency/spatial response. The sensors communicate synchronously with a main processor unit. The array is illuminated by a source, which may be narrow- or broadband, in near or far field. Additional disturbances may be present, in the form of interferers, possibly correlated or coherent with the main signal, and additive noise. The goal is required to steer beam toward the desired signal. Four schemes are presented, each based on the type of prior available information.
Recently, cepstral analysis based on second order statistics and homomorphic filtering techniques have been used in the adaptive decomposition of overlapping, or otherwise, and noise contaminated ECG complexes of moth...
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ISBN:
(纸本)0819422347
Recently, cepstral analysis based on second order statistics and homomorphic filtering techniques have been used in the adaptive decomposition of overlapping, or otherwise, and noise contaminated ECG complexes of mothers and fetals obtained by a transabdominal surface electrodes connected to a monitoring instrument, an interface card, and a PC. Differential time delays of fetal heart beats measured from a reference point located on the mother complex after transformation to cepstra domains are first obtained and this is followed by fetal heart rate variability computations. Homomorphic filtering in the complex cepstral domain and the subuent transformation to the time domain results in fetal complex recovery. However, three problems have been identified with second-order based cepstral techniques that needed rectification in this paper. These are (1) errors resulting from the phase unwrapping algorithms and leading to fetal complex perturbation, (2) the unavoidable conversion of noise statistics from Gaussianess to non-Gaussianess due to the highly non-linear nature of homomorphic transform does warrant stringent noise cancellation routines, (3) due to the aforementioned problems in (1) and (2), it is difficult to adaptively optimize windows to include all individual fetal complexes in the time domain based on amplitude thresholding routines in the complex cepstral domain (i.e. the task of `zooming' in on weak fetal complexes requires more processing time). The use of third-order based high resolution differential cepstrum technique results in recovery of the delay of the order of 120 milliseconds.
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