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42nd Annual International Conference on Parallel processing (ICPP)

作者： Zain-ul-Abdin Ahlander, Anders Svensson, Bertil Halmstad Univ Ctr Res Embedded Syst CERES Halmstad Sweden Saab AB Gothenburg Sweden

ISBN: (纸本)9780769551173

The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in real time. Manycore architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner. In this paper, we evaluate a manycore architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an autofocus criterion calculation and the fast factorized back-projection algorithm, both key components in modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the autofocus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized backprojection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient.

关键词： Manycore architecture Parallel programming Radar signal processing

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Parallel uses for serial arithmetic in signal processors

Parallel uses for serial arithmetic in signal processors

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advanced signal processing algorithms, architectures, and implementations II

作者： Owens, Robert M. Irwin, Mary J. The Pennsylvania State Univ. University Park PA USA

ISBN: (纸本)0819406945

In this paper we consider using 'digit serial' processing to build high performance parallel structures, in particular, parallel signal processors. Digit serial arithmetic processors have digit serial data transmission combined with digit serial computation. Three digit serial arithmetic processors are presented and compared with their digit parallel counterparts. We show that by using a digit serial approach we can achieve a higher throughput than with a digit parallel processor, even though the two processors are structurally similar and have components of similar complexity.

关键词： signal processing

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Naval Research Lab. flex processor for radar signal processing

Naval Research Lab. flex processor for radar signal processi...

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advanced signal processing algorithms, architectures, and implementations II

作者： Alter, James J. Evins, James B. Letellier, J.P. Naval Research Lab. Washinton DC USA

ISBN: (纸本)0819406945

This paper describes a programmable radar signal processor architecture developed at the Naval Research Laboratory (NRL). The design incorporates T.I. TMS320C30 programmable digital signal processor devices, Xilinx programmable gate arrays, TRW FFT devices, and a parallel array of Inmos Transputer microprocessors. The architecture is extremely flexible and is applicable to a wide variety of applications.

关键词： Radar

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Parallel algorithms for automatic target recognition using laser radar imagery

Parallel algorithms for automatic target recognition using l...

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advanced signal processing algorithms, architectures, and implementations 1990

作者： Forman, Arthur v. Sullivan, Daniel J. Chang, Arthur W. Martin Marietta Electronic Systems P.O. Box 628007 OrlandoFL32862-8007 United States

This paper describes two techniques for automatic recognition of surface targets from an airborne platform using an imaging laser radar sensor. The first technique rotates a three-dimensional model of the target in real time to enable a generalized Hough transform to match the ladar image to the target's key discriminating features as a basis for target identification. The second technique uses a variation on minimum average correlation energy filters to perform robust target identification. Examples illustrating the application of these algorithms are presented, along with a description of a real-time implementation of the critical parts of the algorithms on a 40,000-processor systolic array based on the Geometric Arithmetic Parallel Processor (GAPP™) chip. © 1990 SPIE. All rights reserved.

关键词： Optical radar

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Adaptive array beamforming with fixed-point arithmetic matrix inversion using Givens rotations

Adaptive array beamforming with fixed-point arithmetic matri...

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Conference on advanced signal processing algorithms, architectures, and implementations XI

作者： Rabinkin, Dv Song, W vai, MM Nguyen, H MIT Lincoln Lab Lexington MA 02420 USA

ISBN: (纸本)0819441880

Adaptive array systems require the periodic solution of the well-known w = (R) over tilde (-1)v equation in order to compute optimum adaptive array weights. The covariance matrix (R) over tilde is estimated by forming a product of noise sample matrices X : (R) over tilde = (XX)-X-H. The operations-count cost of performing the required matrix inversion in real time can be prohibitively high for a high bandwidth system with a large number of sensors. Specialized hardware may be required to execute the requisite computations in real time. The choice of algorithm to perform these computations must be considered in conjunction with the hardware technology used to implement the computation engine. A systolic architecture implementation of the Givens rotation method for matrix inversion was selected to perform adaptive weight computation. The bit-level systolic approach enables a simple ASIC design and a very low power implementation. The bit-level systolic architecture must be implemented with fixed-point arithmetic to simplify the propagation of data through the computation cells. The Givens rotation approach has a highly parallel implementation and is ideally suited for a systolic implementation. Additionally, the adaptive weights are computed directly from the sample matrix X in the voltage domain, thus reducing the required dynamic range needed in carrying out the computations. An analysis was performed to determine the required fixed-point precision needed to compute the weights for an adaptive array system operating in the presence of interference. Based on the analysis results. it was determined that the precision of a floating-point computation can be well approximated with a 13-bit to 19-bit word length fixed point computation for typical system jammer-to-noise levels. This property has produced an order-of-magnitude reduction in required hardware complexity. A synthesis-based ASIC design process was used to generate preliminary layouts. These layouts were used t

关键词： very large scale integration Chemical elements Computing systems Sensors Statistical analysis Computer architecture Matrices Radar Electroluminescence signal processing

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Homogeneous vLSI structures for high speed digital signal processing using number theoretic techniques 4

Homogeneous VLSI structures for high speed digital signal pr...

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advanced algorithms and architectures for signal processing Iv 1989

作者： Jullien, G.A. Miller, W.C. VLSI Research Group University of Windsor WindsorONN9B 3P4 Canada

Exact computations, performed with residues, occur in Number Theoretic Transforms and Residue Number System implementations. Once thought awkward to implement with standard logic circuits, the application of efficient small lookup tables, constructed with pipelined dynamic ROM's, allows very efficient construction of hardware ideally suited to residue operations. Linear DSP operations that are compute bound (require many arithmetic computations per input/output sample), are best suited for implementation with systolic arrays. For very high throughput operations, bit-level systolic arrays appear to be ideally suited to their implementation. The dynamic ROM's used for the residue computations, are a perfect vehicle for implementing such operations at the bit-level in a systolic architecture. This paper discusses vLSI architectures based on finite ring computations, using linear systolic arrays of small look-up tables. The advantage of this approach is that fixed coefficient multiplication requires no increase in hardware over that required for general addition, and the resulting structure is homogeneous in that only one cell type is required to implement all of the processing functions. Several advantages accrue in the vLSI setting, particularly clock rate increase, ease of testability and natural fault tolerance Three different approaches to implementing the finite ring/field residue calculations are discussed. The first uses a bit-level steering mechanism around small dynamic ROM's;two applications of this technique to digital signal processing are outlined. The other two techniques are based on a redundant binary representation implemented with a pipelined adder configuration, and an iterative solution technique based on neural-like networks. © 1989 SPIE. All rights reserved.

关键词： Iterative methods

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Improving Utilization of Dataflow Unit for Multi-Batch processing

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2024年第1期21卷 1-26页

作者： Fan, Zhihua Li, Wenming Wang, Zhen Yang, Yu Ye, Xiaochun Fan, Dongrui Sun, Ninghui An, Xuejun Chinese Acad Sci State Key Lab Processors Inst Comp Technol Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Chinese Acad Sci Inst Comp Technol 6 South Sci Acad Rd Beijing Peoples R China Univ Chinese Acad Sci 19A Yuquan Rd Beijing Peoples R China

Dataflow architectures can achieve much better performance and higher efficiency than general-purpose core, approaching the performance of a specialized design while retaining programmability. However, advanced application scenarios place higher demands on the hardware in terms of cross-domain and multi-batch processing. In this article, we propose a unified scale-vector architecture that can work in multiple modes and adapt to diverse algorithms and requirements efficiently. First, a novel reconfigurable interconnection structure is proposed, which can organize execution units into different cluster typologies as a way to accommodate different data-level parallelism. Second, we decouple threads within each DFG node into consecutive pipeline stages and provide architectural support. By time-multiplexing during these stages, dataflow hardware can achieve much higher utilization and performance. In addition, the task-based program model can also exploit multi-level parallelism and deploy applications efficiently. Evaluated in a wide range of benchmarks, including digital signal processing algorithms, CNNs, and scientific computing algorithms, our design attains up to 11.95x energy efficiency (performance-per-watt) improvement over GPU (v100), and 2.01x energy efficiency improvement over state-of-the-art dataflow architectures.

关键词： Utilization network-on-chip decoupled architecture batch processing

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Comparison of synthetic-aperture radar autofocus techniques: phase gradient versus subaperture

Comparison of synthetic-aperture radar autofocus techniques:...

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advanced signal processing algorithms, architectures, and implementations II

作者： Calloway, Terry M. Jakowatz Jr., Charles v. Thompson, Paul A. Eichel, Paul H. Sandia Natl. Labs. Albuquerque NM USA

ISBN: (纸本)0819406945

Two methods of focusing synthetic aperture radar (SAR) images are compared. Both a conventional subaperture cross-correlation method and a new phase gradient autofocus (PGA) algorithm developed at Sandia National Laboratories are shown to perform well if high-order phase errors are not present. With the introduction of significant high-order phase errors [e.g., due to uncompensated platform motion], both algorithms suffer a loss in performance. However, relative performance degradation is less for PGA than for the subaperture focusing technique. An explanation is presented for the observed behavior of the two autofocus techniques.

关键词： Radar Imaging

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Efficient computation of densely sampled wavelet transforms

Efficient computation of densely sampled wavelet transforms

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advanced signal processing algorithms, architectures, and implementations II

作者： Jones, Douglas L. Baraniuk, Richard G. Univ. of Illinois/Urbana-Champaign Urbana IL USA

ISBN: (纸本)0819406945

An efficient algorithm is presented for computing the continuous wavelet transform and the wideband ambiguity function on a sample grid with uniform time spacing but arbitrary sampling in scale. The method is based on the chirp z-transform and requires the same order of computation as constant-bandwidth analysis techniques, such as the short-time Fourier transform and the narrowband ambiguity function. An alternative spline approximation method which is more efficient when the number of scale samples is large is also described.

关键词： signal processing

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Mathematical representation of joint time-chroma distributions

Mathematical representation of joint time-chroma distributio...

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Proceedings of the 1999 advanced signal processing algorithms, architectures, and implementations IX

作者： Wakefield, Gregory H. Univ of Michigan Ann Arbor United States

Originally coined by the sensory psychologist Roger Shepard in the 1960's, chroma transforms frequency into octave equivalence classes. By extending the concept of chroma to chroma strength and how it varies over time, we have demonstrated the utility of chroma in simplifying the processing and representation of signals dominated by harmonically-related narrowband components. These investigations have utilized an ad hoc procedure for calculating the chromagram from a given time-frequency distribution. The present paper is intended to put this ad hoc procedure on more sound mathematical ground.

关键词： Speech processing

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