The real time implementation of an efficient signal compression technique, vector Quantization (vQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit le...
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The real time implementation of an efficient signal compression technique, vector Quantization (vQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic vLSI architectures which offer an attractive solution to this problem. These architectures are based on a bit serial, word parallel approach and high performance and efficiency can be achieved for vQ applications of a wide range of bandwidths. Compared with their bit parallel counterparts, these bit serial circuits provide better alternatives for vQ implementations in terms of performance and cost.
Details are presented of the IRIS synthesis system for high-performance digital signalprocessing. This tool allows non-specialists to automatically derive vLSI circuit architectures from high-level, algorithmic repre...
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Details are presented of the IRIS synthesis system for high-performance digital signalprocessing. This tool allows non-specialists to automatically derive vLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit.
The aim of the paper is to estimate the contribution of the polarization diversity in high frequency (3 - 30 MHz) direction finding systems. We first describe the peculiarities of H.F. propagation and the resulting si...
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ISBN:
(纸本)0819416207
The aim of the paper is to estimate the contribution of the polarization diversity in high frequency (3 - 30 MHz) direction finding systems. We first describe the peculiarities of H.F. propagation and the resulting signal model involved in computer simulations. Next, we analyze the behavior of some particular direction finding systems using linear and circular geometries and polarization diversity. Some algorithms (non linear frequential analysis, M.U.S.I.C.) are tested in several conditions (narrowband or broadband signals, polarization filtering reiterated or no, sub-sampling). Theoretical and experimental results show that polarization diversity based upon the knowledge of the antenna complex responses improves greatly the efficiency of direction finding.
Artificial Neural Networks are an interesting solution for several real-time applications in the area of signal and image processing, in particular since recent advances in vLSI integration technologies allow for effi...
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ISBN:
(纸本)0819416207
Artificial Neural Networks are an interesting solution for several real-time applications in the area of signal and image processing, in particular since recent advances in vLSI integration technologies allow for efficient hardware realizations. The use of dedicated circuits implementing the neural networks in mission-critical applications requires a high level of protection with respect to errors due to faults to guarantee output credibility and system availability. In this paper, the problem of concurrent error detection in dedicated neural networks is discussed by adopting an algorithm-based approach to check the inner product, i.e., the most of the computation performed in the neural network. Effectiveness and efficiency of this technique is shown and evaluated for the widely-used classes of neural paradigms.
The Complex Arithmetic Processor (CAP) is a high performance, single chip Digital signal Processor optimized for communication signalprocessing operations. The CAP vLSI provides the communication system building bloc...
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ISBN:
(纸本)0819416207
The Complex Arithmetic Processor (CAP) is a high performance, single chip Digital signal Processor optimized for communication signalprocessing operations. The CAP vLSI provides the communication system building block necessary to meet the increased signalprocessing requirements of complex modulation types, voice and image compression while maintaining the requirement for small, low power implementations. The chip is intended for high speed, low power digital communication system applications such as hand held spread spectrum communications systems. The CAP architecture has been developed specifically for the complex arithmetic functions required in communication signalprocessing. The CAP is a software programmable, highly integrated parallel array of processors containing the arithmetic resources, memories, address generation, bit manipulation and logic functions necessary to support the sophisticated processing required in advanced communication equipment. The CAP executes a 1024 point complex Fast Fourier Transform in 131 microseconds.
This paper describes research into a high speed image processing system using parallel digital signal processors for the processing of electro-optic images. The objective of the system is to reduce the processing time...
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ISBN:
(纸本)0819416207
This paper describes research into a high speed image processing system using parallel digital signal processors for the processing of electro-optic images. The objective of the system is to reduce the processing time of non-contact type inspection problems including industrial and medical applications. A single processor can not deliver sufficient processing power required for the use of applications hence, a MIMD system is designed and constructed to enable fast processing of electro-optic images. The Texas Instruments TMS320C40 digital signal processor is used due to its high speed floating point CPU and the support for the parallel processing environment. A custom designed vISION bus is provided to transfer images between processors. The system is being applied for solder joint inspection of high technology printed circuit boards.
A number of adaptive condition number estimators have been proposed in the past to dynamically estimate the sensitivity of the coefficient matrix of a linear systems of equations. Applications of these techniques ofte...
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ISBN:
(纸本)0819416207
A number of adaptive condition number estimators have been proposed in the past to dynamically estimate the sensitivity of the coefficient matrix of a linear systems of equations. Applications of these techniques often arise in the context of signalprocessing, where the information matrix is being updated with rank-one modifications. various schemes, such as ACE, ALE and ICE, were proposed to cope with this problem. In this paper, we will briefly review the past work, and show how the small-sample condition estimator can be used in an adaptive manner.
The concern here is of retrieving damped harmonics and polynomial phase signals in the presence of additive noise. The damping function is not limited to the exponential model, and in certain cases, the additive noise...
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ISBN:
(纸本)0819416207
The concern here is of retrieving damped harmonics and polynomial phase signals in the presence of additive noise. The damping function is not limited to the exponential model, and in certain cases, the additive noise does not have to be white. Three classes of algorithms are presented, namely DFT based, Kumaresan-Tufts type extensions, and subspace variants including the MUSIC algorithm. Preference should be based on the available data length and frequency separations. In addition, retrieval of self coupled damped harmonics, which may be present when nonlinearities exist in physical systems, is investigated. Simulation examples illustrate main points of the paper.
We present an algorithm-based fault tolerant scheme for QR decomposition, that extends the well-known Gentleman-Kung-McWhirter triangular systolic array architecture. Assuming that the array is subject to transient fa...
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ISBN:
(纸本)0819416207
We present an algorithm-based fault tolerant scheme for QR decomposition, that extends the well-known Gentleman-Kung-McWhirter triangular systolic array architecture. Assuming that the array is subject to transient faults, widely separated in time and each affecting a single processor, we give an algorithm that corrects the full triangular array with computational overhead equivalent, on average, to the interpolation of a single extra vector into the data stream.
The Rapid Prototyping of Application Specific signal Processors (RASSP) program has as its goal the dramatic improvement of the process by which signal processors are specified, designed, documented, manufactured, and...
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ISBN:
(纸本)0819416207
The Rapid Prototyping of Application Specific signal Processors (RASSP) program has as its goal the dramatic improvement of the process by which signal processors are specified, designed, documented, manufactured, and supported. A key part of the RASSP process is the method of architecture selection. An architecture overview is presented, together with a discussion of architecture classification, architecture evaluation factors, and signalprocessing flow. Two important architecture support aspects are briefly discussed: open systems architecture and integrated diagnostics. Recommendations for preferred approaches and rules of thumb for architecture selection are given. Finally, the RASSP architecture selection process is outlined, including a discussion of a standard hardware/software module interface.
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