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检索条件"任意字段=Advanced Signal Processing: Algorithms, Architectures, and Implementations V"

共 472 条记录，以下是321-330 订阅

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Compilation time analysis to minimize run-time overhead in preemptive scheduling on multiprocessors

Compilation time analysis to minimize run-time overhead in p...

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advanced signal processing: algorithms, architectures, and implementations v

作者： Wauters, Piet Lauwereins, Rudy Peperstraete, J. Katholieke Univ. Leuven Heverlee Belg

ISBN: (纸本)0819416207

This paper describes a scheduling method for hard real-time Digital signal processing (DSP) applications, implemented on a multi-processor. Due to the very high operating frequencies of DSP applications (typically hundreds of kHz) runtime overhead should be kept as small as possible. Because static scheduling introduces very little run-time overhead it is used as much as possible. Dynamic pre-emption of tasks is allowed if and only if it leads to better performance in spite of the extra run-time overhead. We essentially combine static scheduling with dynamic pre-emption using static priorities. Since we are dealing with hard real-time applications we must be able to guarantee at compile-time that all timing requirements will be satisfied at run-time. We will show that our method performs at least as good as any static scheduling method. It also reduces the total amount of dynamic pre-emptions compared with run time methods like deadline monotonic scheduling.

关键词： Digital signal processing

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Pipelining multiple singular value decomposition (SvDs) on a single processor array

Pipelining multiple singular value decomposition (SVDs) on a...

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advanced signal processing: algorithms, architectures, and implementations v

作者： Kota, Kishore Cavallaro, Joseph R. Rice Univ. Houston TX USA

ISBN: (纸本)0819416207

We present a new family of architectures for processor arrays to implement Jacobi SvD which allow systolic loading and unloading of input and result matrices. Unlike most of the previous SvD arrays in the literature, our architectures do not require special handling of external I/O and hence are closer to the traditional concept of systolic architectures. The boundary processors communicate with the host the same way any of the interior processors communicate with their neighbors. The arrays are surprisingly uniform and simple. The various architectures in the family represent different throughput-hardware tradeoffs corresponding to the degree to which the multiple sweeps have been unrolled and determine the number of independent SvDs which may be pipelined on the array. We achieved systolic loading by using the flexibility provided by the cyclic Jacobi method on the order in which pivot pairs may be chosen. The array operates on the matrix data even as it is being loaded. Once the pipeline is full, the ordering is very similar to odd-even ordering. Our ordering is equivalent to cyclic-by-rows ordering and hence the algorithm is guaranteed to converge. Our systolic loading scheme is very important in an I/O limited system, since it allows more communication to occur in parallel, where the communication includes the loading and unloading operations. The array with the highest throughput in our family of architectures, which implement one-sided Jacobi (either Hestenes' method or Eberlein and Park's method), is a linear array of processors with unidirectional links between neighbors. The architectures with lower throughput require fewer processors connected in a ring, allowing data to recirculate among the processors. The input matrix is loaded one column at a time from the left and the results stream out one column at a time from the right.

关键词： Pipeline processing systems

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Parallel architectures for computing the Hough transform and CT image reconstruction

Parallel architectures for computing the Hough transform and...

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Proceedings of the 1994 International Conference on Application Specific Array Processors

作者： Lin, L. Jain, v.K. Univ of South Florida Tampa United States

This paper discusses high-speed array implementations of two image processing algorithms, namely the 'Hough transform for Detection of line segments', and 'Backprojection in CT image reconstruction'. A multi-chip-module (MCM) construction is proposed consisting of three types of chips, a high speed multi-function nonlinear chip, a flexible Multiply-Accumulate chip, and an image kernel chip. Called v-array, it can be configured to have eight HOUGH modules, so as to produce the Hough transform of a 1024 × 1024 image in an estimated 13 ms in 2.0 micron CMOS technology (6.6 ms in 1.0 micron CMOS technology). Similarly, a v-array MCM can accommodate eight CT modules, which can produce the backprojected image in 209 ms in 2.0 micron CMOS technology (105 ms in 1.0 micron CMOS technology). To gain a significant speed advantage, we have developed an advanced multi-function cell for performing any one of four nonlinear operations: (1) square-root, (2) reciprocal, (3) sine/cosine, and (4) arctangent - - all realized in a single chip, accessible on a selectable basis. A 16 bit four-function 'one cycle' vLSI chip, fabricated in 2.0 micron CMOS technology, is presently available which outputs a new result every clock cycle. Using this nonlinear cell and two other cells, an application level Hough transform module and a CT module are presented.

关键词： Parallel processing systems

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Parallel architectures for real-time control

Parallel architectures for real-time control

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IEE Colloquium on High Performance Applications of Parallel architectures

作者： M.O. Tokhi M.A. Hossain M.J. Baxter P.J. Fleming Department of Automatic Control and Systems Engineering University of Sheffield Sheffield UK

The authors present an investigation into the utilisation of parallel computing techinques for real-time simulation and control of a flexible beam structure in transverse vibration. The performance demands of modern control systems require the employment of complex algorithms with demanding operations which, in turn, leads to shorter sampling times. Therefore, real-time performance in control applications where the use of advanced control methods is warranted becomes difficult to accomplish. Many demanding complex control processes cannot be satisfactorily realised with conventional uni-processor and multi-processor systems. Previous investigations have demonstrated the limitations of employing only transputers for real-time implementations in control applications. Alternative strategies where multi-processor based systems are employed, utilising digital signal processing (DSP) and parallel processing techniques, could provide suitable methodologies.< >

关键词： Digital control Simulation Parallel architectures Real time systems signal processing Structural engineering Computer aided engineering

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Parallel architecture for universal digital signal processing

Parallel architecture for universal digital signal processin...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： v.K. Jain H. Hikawa Department of Electrical Engineering University of South Florida Tampa FL USA Department of Computer & Sc. and Intelligent Sys. Oita University Oita Japan

The paper describes a parallel architecture for universal digital signal processing. This architecture uses not only multiply-accumulate but also nonlinear operations, such as reciprocal, squareroot, exponential, sine/cosine, etc. Several advanced algorithms can thus be mapped to this array architecture. Specifically, the paper focuses attention on two very diverse algorithms, namely the fast Fourier transform and the matrix LU decomposition. Only two types of cells are used in the architecture; these are the Universal Multiply-Subtract-Add cell (UMSA) and the Universal Nonlinear cell (UNL). Both MA and nonlinear operations are performed in hardware, so that the operation times are on the order of chip-clock cycle times. The use of only two types of cells makes the architecture highly suitable for wafer scale integration. It is interesting to note that the same resources on the wafer are used for configuring it to either the FFT algorithm or the LU decomposition algorithm.< >

关键词： Parallel architectures Digital signal processing signal processing algorithms Computer architecture Pipelines Hardware Wafer scale integration Application software Image processing Fast Fourier transforms

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Parallel architectures for computing the Hough transform and CT image reconstruction

Parallel architectures for computing the Hough transform and...

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International Conference on Application Specific Array Processors

作者： L. Lin v.K. Jain Department of Electrical Engineering University of South Florida Tampa FL USA

This paper discusses high-speed array implementations of two image processing algorithms, namely the 'Hough transform for detection of line segments', and 'backprojection in CT image reconstruction'. A multi-chip-module (MCM) construction is proposed consisting of three types of chips, a high speed multi-function nonlinear chip, a flexible multiply-accumulate chip, and an image kernel chip. Called v-array, it can be configured to have eight Hough modules, so as to produce the Hough transform of a 1024/spl times/1024 image in an estimated 13 ms in 2.0 micron CMOS technology (6.6 ms in 1.0 micron CMOS technology). Similarly, a v-array MCM can accommodate eight CT modules, which can produce the backprojected image in 209 ms in 2.0 micron CMOS technology (105 ms in 1.0 micron CMOS technology). To gain a significant speed advantage, we have developed an advanced multi-function cell for performing any one of four nonlinear operations: square-root, reciprocal, sine/cosine, and arctangent-all realized in a single chip, accessible on a selectable basis. A 16 bit four-function "one cycle" vLSI chip, fabricated in 2.0 micron CMOS technology, is presently available which outputs a new result every clock cycle. Using this nonlinear cell and two other cells, an application level Hough transform module and a CT module are presented.< >

关键词： Parallel architectures Concurrent computing CMOS technology Computed tomography Image processing Image segmentation Image reconstruction Kernel Performance gain very large scale integration

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advanced signal processing algorithms, architectures, and implementations Iv

Advanced Signal Processing Algorithms, Architectures, and Im...

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advanced signal processing algorithms, architectures, and implementations Iv 1993

The proceedings contain 45 papers. The topics discussed include: recent advances in nonstationary signal analysis: time-varying higher-order spectra and multilinear time-frequency signal analysis;real-time radar signal processing for autonomous aircraft landing;radon transform-based velocity estimation of vehicles with linear arrays;coherent signal-subspace processing for near-field broad-band source localization;performance analysis of the subspace-based DOA estimator in the presence of unknown noise;numerical integration of PDEs by discrete passive modeling of physical systems;time-recursive computation and real-time parallel architectures, with application on the modulated lapped transform;and discrete frequency estimation using parametric filtering and the contraction mapping method.

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UNIFYING PARAMETRIZED vLSI JACOBI algorithms AND architectures 4

UNIFYING PARAMETRIZED VLSI JACOBI ALGORITHMS AND ARCHITECTUR...

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4TH CONF ON advanced signal processing algorithms, architectures, AND implementations

作者： DEPRETTERE, EF MOONEN, M Delft Univ. of Technology (Netherlands) Katholieke Univ. Leuven (Belgium)

ISBN: (纸本)0819412767

Implementing Jacobi algorithms in parallel vLSI processor arrays is a non-trivial task, in particular when the algorithms are parametrized with respect to size and the architectures are parametrized with respect to space-time trade-offs. The paper is concerned with an approach to implement several time-adaptive Jacobi-type algorithms on a parallel processor array, using only Cordic arithmetic and asynchronous communications, such that any degree of parallelism, ranging from single-processor up to full-size array implementation, is supported by a `universal' processing unit. This result is attributed to a gracious interplay between algorithmic and architectural engineering.

关键词： Array processing signal processing very large scale integration Computer aided design Parallel computing Process control MATLAB Computer architecture Detection and tracking algorithms Electrical engineering

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SYSTEMATIC CONSTRUCTION OF ORDER-RECURSIvE LS ESTIMATION algorithms WITH ELEMENTARY ORTHOGONAL TRANSFORMATIONS 4

SYSTEMATIC CONSTRUCTION OF ORDER-RECURSIVE LS ESTIMATION ALG...

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4TH CONF ON advanced signal processing algorithms, architectures, AND implementations

作者： LING, F Motorola (United States)

ISBN: (纸本)0819412767

This paper demonstrates that order-recursive least squares (ORLS) algorithms based on orthogonal transformations and hyperbolic transformations can be systematically constructed in two steps. The first step is to determine the structure of the ORLS algorithm according to the property of the data vector in the LS estimation and the requirements to the output. The second step is to determine the proper implementation of building blocks of the ORLS structure using orthogonal or hyperbolic transformations. The canonical ORLS structure and some possible orthogonal/hyperbolic implementations of their building blocks are presented. It is also shown that some of the orthogonal transformations are only applicable to certain types of ORLS structures and not to others.

关键词： Algorithm development Error analysis Detection and tracking algorithms Digital signal processing Expectation maximization algorithms Statistical analysis Factor analysis Magnesium Roads Telecommunications

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ERROR PROPAGATION OF SOME FAST RLS algorithms 4

ERROR PROPAGATION OF SOME FAST RLS ALGORITHMS

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4TH CONF ON advanced signal processing algorithms, architectures, AND implementations

作者： QIAO, SZ McMaster Univ. (Canada)

ISBN: (纸本)0819412767

The fast recursive least squares (RLS) algorithms have wide applications in signal processing and control. They are computationally efficient. Thus their stability is of major concern. In this paper, we investigate the error propagation and stability of some typical fast RLS algorithms. Through a random example, we show that a typical conventional fast RLS algorithm is weakly unstable in computing both the residuals and the gain vectors and a QR based algorithm is expected to be weakly stable in computing the residuals but weakly unstable in computing the gain vectors. We propose an error correction scheme for computing the gain vectors.

关键词： Algorithm development Condition numbers MATLAB Lead Process control signal processing Analytical research

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