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Real-time implementation of the multistage detector for next generation wideband CDMA systems

Real-time implementation of the multistage detector for next...

引用

Proceedings of the 1999 advanced signal processing algorithms, architectures, and implementations IX

作者： Xu, Gang Cavallaro, Joseph R. Rice Univ Houston United States

The multistage detection algorithm has been widely accepted as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time implementation of this detection algorithm in the uplink system, where we have achieved both high performance in the interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. We recode the estimation bits, mapping from ±1 to 0 and ±2. Bypassing all the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. The system delay of a three-stage detector can be reduced by half with satisfactory bit error rate. We also propose a vLSI implementation of this algorithm that has the potential of real-time performance. The detector handling up to eight users with 12-bit fixed point precision was fabricated using a 1.2 μm CMOS technology.

关键词： Digital signal processing

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Application of canonical correlation analysis in detection in presence of spatially correlated noise

Application of canonical correlation analysis in detection i...

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advanced signal processing algorithms, architectures, and implementations II

作者： Chen, Wei G. Reilly, James P. Wong, Kon M. McMaster Univ. Hamilton Ontario Canada

ISBN: (纸本)0819406945

A new approach to the problem of detecting the number of signals in unknown colored noise environments is presented. Based on an assumption that the noise is correlated only over a limited spatial range, the principle of canonical correlation analysis is applied to the outputs of two spatially-separated arrays. The number of signals is determined by testing the significance of the sample canonical correlation coefficients. The new method is shown to work well in both white and unknown colored noise situations and does not require any subjective threshold setting. Instead, a set of threshold values are generated according to a specified or desired false alarm rate. Simulation results are included to illustrate the comparative performance of the proposed canonical correlation technique (CCT), versus the well-known AIC and MDL criteria, in colored noise. It is found that the performance of the AIC and MDL criteria degrade very rapidly as the degree of color in the noise increases. On the other hand, the performance of the CCT method is relatively insensitive with respect to variations in degree of color.

关键词： signal processing

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Computing the generalized singular value decomposition on the connection machine

Computing the generalized singular value decomposition on th...

引用

advanced signal-processing algorithms, architectures, and implementations

作者： Park, Haesun Ewerbring, L.Magnus Univ of Minnesota Minneapolis United States

A new algorithm for computing the generalized singular value decomposition that diagonalizes two matrices is introduced. First, two existing algorithms are studied, one due to Paige and the other to Hari and veselic. The former requires only orthogonal plane transformations, resulting in two matrices with parallel rows. The latter employs nonsingular (not necessarily orthogonal) transformations to directly diagonalize the two data matrices. For many applications, it is preferable to be given both the diagonal matrices and the transformation matrices explicitly. Our algorithm has the advantages that the nonsingular transformation is readily available, computation of transformations is simple, convergence test is efficient in a parallel computing environment, and the condition of each nonsingular transformation can be controlled. We present implementation results, obtained on a Connection Machine 2, to compare our new algorithm with that of Paige.

关键词： signal processing

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High-performance FFT implementation on the BOPS ManArray parallel DSP

High-performance FFT implementation on the BOPS ManArray par...

引用

Proceedings of the 1999 advanced signal processing algorithms, architectures, and implementations IX

作者： Pitsianis, Nikos P. Pechanek, Gerald BOPS Inc Chapel Hill United States

We present a high performance implementation of the FFT algorithm on the BOPS ManArray parallel DSP processor. The ManArray we consider for this application consists of an array controller and 2 to 4 fully interconnected processing elements. To expose the parallelism inherent to an FFT algorithm we use a factorization of the DFT matrix in Kronecker products, permutation and diagonal matrices. Our implementation utilizes the multiple levels of parallelism that are available on the ManArray. We use the special multiply complex instruction, that calculates the product of two complex 32-bit fixed point numbers in 2 cycles (pipelinable). Instruction level parallelism is exploited via the indirect very Long Instruction Word (ivLIW). With an ivLIW, in the same cycle a complex number is read from memory, another complex number is written to memory, a complex multiplication starts and another finishes, two complex additions or subtractions are done and a complex number is exchanged with another processing element. Multiple local FFTs are executed in Single Instruction Multiple Data (SIMD) mode, and to avoid a costly data transposition we execute distributed FFTs in Synchronous Multiple Instructions Multiple Data (SMIMD) mode.

关键词： Parallel processing systems

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FPGA Based Image processing: A Comparative Study of Software-Centric and Hardware-Accelerated Approaches

FPGA Based Image Processing: A Comparative Study of Software...

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2024 International Conference on Smart Electronics and Communication Systems, ISENSE 2024

作者： Parameswaran, P.N. Janardan, S. Nair, Siddharth R Thejaswitha, K.T. Nikhil, M. Adersh, v.R. College of Engineering Trivandrum Dept of Electronics and Communication Thiruvananthapuram India

ISBN: (纸本)9798331528126

This work compares two different approaches to image processing algorithm implementation in Zynq Zybo and Zedboard Field Programmable Gate Array (FPGA) boards. There are three main phases for the study, namely, Hardware-Accelerated Image processing (HAIP), Software-Centric Image processing (SCIP), and an in-depth analysis of their corresponding performance metrics. Image processing algorithms were implemented in the SCIP phase, exclusively using the Zynq processing System (PS). On the other hand, the HAIP phase comprised creating distinct Intellectual Properties (IPs) for image processing tasks and integrating them with the Zynq PS through Direct Memory Access (DMA) and the advanced eXtensible Interface (AXI) *** all assessed techniques, HAIP considerably outperformed SCIP in terms of processing time, for different image sizes, across both Zynq Zybo and Zedboard. On the other hand, as SCIP is software-centric, it showed minimal resource utilization and lower power consumption than HAIP, which showed higher resource utilization and power consumption. However, both methods produced processed images that were similar, highlighting the stability and dependability of FPGA-based image processing implementations. A comparative analysis between Zynq Zybo and Zedboard reveals insights into how different FPGA architectures impact the performance and resource utilization of image processing implementations. This work offers insights into the trade-offs between hardware-accelerated and software-centric approaches to image processing on FPGA platforms, guiding future design decisions for practical uses. © 2024 IEEE.

关键词： Image analysis

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Kernel synthesis for generalized time-frequency distributions using the method of projections onto convex sets

Kernel synthesis for generalized time-frequency distribution...

引用

advanced signal-processing algorithms, architectures, and implementations

作者： Oh, Seho Marks II, R.J. Atlas, L.E. Pitton, J.W. Univ of Washington Seattle United States

The kernel in Cohen's generalized time-frequency representation (GTFR) requires is chosen in accordance to certain desired performance attributes. Properties of the kernel are typically expressed as constraints. We establish that many commonly used constraints are convex in the sense that all allowable kernels satisfying a given constraint form a convex set. Thus, for a given set of constraints, the kernel can be designed by alternately projecting among these sets. If there exists a nonempty intersection among the constraint sets, then the theory of projection onto convex sets (POCS) guarantees convergence to a point in the intersection. If the constraints can be partitioned into two sets, each with a nonempty intersection, the POCS guarantees convergence to a kernel that satisfies the inconsistent constraints with minimum mean square error.

关键词： signal processing

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Transient detection in the presence of strong narrow band interference via Wigner-ville spectrum

Transient detection in the presence of strong narrow band in...

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advanced signal-processing algorithms, architectures, and implementations

作者： Marinovich, Nenad M. Roytman, Leonid M. City Univ of New York New York United States

We consider the problem of detecting a known Gaussian random transient in the presence of a strong, known, random, Gaussian, narrowband interference. This can be regarded as a special case of the classical problem of detecting a known Gaussian random signal in known Gaussian colored noise. There exists a standard solution for such a problem, based on the classical optimum detector for random signals in noise. However, such a detector does not explicitly use the non-stationary character of the signal as a priori available information. Reformulation of the optimum detection in the time-frequency plane allows one to exploit this distinguishing signal feature and suppress the stationary interference and noise. This is accomplished here by use of the Wigner-ville signal representation and an optimum signal/noise subspace decomposition that maximizes the transient signal to noise ratio. The new detection procedure eliminates the subspace where major part of the energy of random noise sample will fall while retaining almost all of the signal energy. In this fashion, a gain in the output signal to noise ratio is achieved as verified by simulations.

关键词： signal processing

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Instantaneous frequency and kernel requirements for discrete time-frequency distributions

Instantaneous frequency and kernel requirements for discrete...

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advanced signal-processing algorithms, architectures, and implementations

作者： Jeong, Jechang Cunningham, Gregory S. Williams, William J. Univ of Michigan Ann Arbor United States

In this paper, we introduce a new definition for the instantaneous frequency of a discrete-time analytic signal. Unlike the existing definition which uses only two data samples around a particular time, this method utilizes all the data samples for estimating the instantaneous frequency. We prove that this quantity is identical to the average frequency evaluated at the particular time in the discrete-time TFD. This property is consistent with the analogous continuous-time property. We also derive requirements on the discrete-time kernel needed to satisfy this property. Using computer-generated signals and real data, performance comparisons are made between the proposed approach and the existing one.

关键词： signal processing

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Integrated Memory/Network architectures for cluster-organized, parallel DSP architectures

Integrated Memory/Network architectures for cluster-organize...

引用

1998 IEEE Symposium on IC/Package Design Integration

作者： Tewksbury, SK Gandakota, v Devabattini, K Adabala, P W Virginia Univ Morgantown WV 26506 USA

ISBN: (纸本)081868433X

The capabilities of switched networks for parallel and distributed computers are evolving rapidly towards networks with various forms of intelligence in support of parallel execution of programs. This paper presents a perspective on intelligent networks, including reconfiguration of the network to adapt to the needs of successive computational algorithms being performed as part of an overall problem, for clusters containing a modest number of digital signal processors (DSPs), Scalability of the overall parallel DSP-based computer is achieved by adding these cluster nodes. It is suggested that there are many operating system functions which might be directly integrated into such an intelligent network, including adapting those operating system functions according to the needs of the specific tasks being performed. The viewpoint presented here is based on a reconfigurable system using FPGAs and being constructed for image processing applications to study opportunities for integration of such intelligent networks into future silicon vLSI components, including advanced packaging such as multi-chip modules (MCMs), The packaging limitations present the greatest barrier to aggressive development of such networks, with active substrate MCMs implementing the network function providing the greatest flexibility and performance.

关键词： digital signal processor arrays intelligent networks Parallel computing clusters reconflgurable computers

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High throughput, low cost, fully pipelined architecture for AES crypto chip

High throughput, low cost, fully pipelined architecture for ...

引用

2006 Annual India Conference, INDICON

作者： Iyer, Nalini C. Anandmohan, P.v. Poornaiah, D.v. Kulkarni, v.D. IEEE Dept. of E and C BVBCET Hubli India ECIL Bangalore India ITI Bangalore India CG-Coreel Bangalore India

ISBN: (纸本)1424403707

Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms. Several papers described efficient architectures for ASICs and FPGAs. various approaches for efficient hardware implementation of the advanced Encryption Standard algorithm based on architectural optimization and algorithmic optimizationfor different modes are discussed and implemented. This paper proposes Compact, Memory less, high-speed hardware architectures for the Rijndael AES Encryptor/Decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and subpipelining. Speed is Increased by processing multiple rounds simultaneously at the cost of increased area. Algorithmic optimization exploits algorithmic strength inside each round unit. various methods such as Resource sharing and Common sub expression elimination method for realizing various transformations in each round unit are presented to reduce the critical path and area issues between encryptor and decryptor. advantage of sub-pipelining can be further explored by eliminating the unbreakable delay incurred by look-up tables in the conventional approaches, the widely used implementation of S-box, which uses combinational logic only. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic such as multiplication and inversion.. Our technique involves mapping field elements to a composite field representation and a representation technique which minimizes the computation cost of the relevant arithmetic. Our method results in a very compact and fast gate circuit for Rijndael encryption and decryption The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle The performance results for various architectural designs su

关键词： Throughput

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