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Accelerated AES implementations via generalized instruction set extensions

Accelerated AES implementations via generalized instruction ...

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作者： Elbirt, A.J. Department of Computer Science University of Massachusetts Lowell Lowell MA 01854 United States Department of Computer Science University of Massachusetts Lowell One University Avenue Lowell MA 01854 United States

Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers, including the advanced Encryption Standard (AES), have been proposed and implemented, using a wide and varied range of functional operations. Existing microprocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) processor cores presents the opportunity to augment existing datapaths with instruction set extensions to add acceleration modules in the form of new instructions. We will present a general purpose instruction set extension to a 32-bit SPARC v8 compatible processor core that accelerates the performance of Galois Field fixed field constant multiplication, a core element of the AES algorithm. This extension will be shown to accelerate AES encryption versus pure software implementations at a small hardware cost. This matches the improvement demonstrated in previously proposed AES-specific instruction set extensions while maintaining a generalized implementation format capable of supporting other algorithms that use Galois Field fixed field constant multiplication. © 2008 - IOS Press and the authors. All right reserved.

关键词： Cryptography

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Quantifying the improvement in energy savings for LTE eNodeB baseband subsystem with technology scaling and multi-core architectures

Quantifying the improvement in energy savings for LTE eNodeB...

引用

18th National Conference on Communications, NCC 2012

作者： Boyapati, Hari Krishna Rajakumar, R.v. Chakrabarti, Saswat G S S School of Telecommunications Indian Institute of Technology Kharagpur 721302 India Rajiv Gandhi University of Knowledge Technologies Campus of IIITH Gachibowli Hyderabad - 500032 India

ISBN: (纸本)9781467308168

Recent wireless broadband cellular standards are aimed at making provisions for supporting very high data rate applications in limited available bandwidth. The most sophisticated as well as computationally complex subsystem of a transceiver of any such system is the baseband processing part of the system. A multi-core processor is typically needed to provide the required computational power for implementing the complex baseband processing subsystem such as that of LTE transceiver. The energy consumption in the baseband part of subsystem is a very significant component of the total energy expenditure of a cellular radio system, particularly when system employs MIMO and advanced vLSI state of art. This paper aims at reducing the energy consumption and also quantify the achievable energy savings by applying the recent trends in vLSI such as CMOS technology scaling and usage of new heterogeneous multi-core architectures specific to signal processing. To be able to explore and apply these energy efficient techniques, we have first estimated the energy consumption in LTE baseband functions then we have explored possible energy savings obtained from technology scaling and optimum heterogeneous combination of architectures for mapping baseband algorithms. © 2012 IEEE.

关键词： Energy utilization

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Translation, rotation and scaling invariant object and texture classification using polyspectra

Translation, rotation and scaling invariant object and textu...

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advanced signal-processing algorithms, architectures, and implementations

作者： Tsatsanis, Michail K. Giannakis, Georgios B. Univ of Virgina Charlottesville United States

The problem addressed in this paper is the detection and classification of deterministic objects and random textures in a noisy scene. An energy detector is developed in the cumulant domain, by exploiting the noise insensitivity of higher-order statistics. An efficient implementation of this detector is described, using matched filtering. Its performance is analyzed using asymptotic distributions in a binary hypothesis testing framework. Object and texture classifiers are derived using higher-order statistics. They are minimum distance classifiers in the cumulant domain, and can be efficiently implemented using a bank of matched filters. Further, they are robust to additive Gaussian noise and insensitive to object shifts. Extensions, which can handle object rotation and scaling are also discussed. An alternate texture classifier is derived from a ML viewpoint, that is more efficient at the expense of complexity. The application of these algorithms to texture modeling is shown and consistent parameter estimators are obtained. Simulations are shown for both the object and the texture classification problems.

关键词： Image processing

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Minimum-phase LU factorization preconditioner for Toeplitz matrices

Minimum-phase LU factorization preconditioner for Toeplitz m...

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advanced signal processing algorithms, architectures, and implementations II

作者： Ku, Ta-Kang Kuo, C.-C.J. Univ. of Southern California Los Angeles CA USA

ISBN: (纸本)0819406945

A new preconditioner is proposed for the solution of an N × N Toeplitz system TNx = b, where TN can be symmetric indefinite or nonsymmetric, by preconditioned iterative methods. The preconditioner FN is obtained based on factorizing the generating function T(z) into the product of two terms corresponding, respectively, to minimum-phase causal and anticausal systems and therefore called the minimum-phase LU (MPLU) factorization preconditioner. Due to the minimum-phase property, F N-1 is bounded. For rational Toeplitz TN with generating function T(z) = A(z-1)/B(z-1) + C(z)/D(z), where A(z), B(z), C(z), and D(z) are polynomials of orders p1, q1, p2, and q2, we show that the eigenvalues of FN-1TN are repeated exactly at 1 except at most α F outliers, where αF depends on p1, q1, p2, q2, and the number approximately ega of the roots of T(z) = A(z-1)D(z) + B(z-1)C(z) outside the unit circle. A preconditioner KN in circulant form generalized from the symmetric case is also presented for comparison.

关键词： signal processing

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A Cross Layer Design for Performance Enhancements in LTE-A System

A Cross Layer Design for Performance Enhancements in LTE-A S...

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IEEE International Conference on Wireless Communications, signal processing and Networking (WiSPNET)

作者： Gandhi, v. Sharmila Maheswaran, B. Mepco Schlenk Engn Coll Dept ECE Sivakasi India

ISBN: (纸本)9781467393379

Cross-layer design with respect to reference layered architecture is the design of algorithms, protocols and architectures that utilize an available set of interlayer exchanges a superset of the standard interfaces provided by the reference layered architecture. The cross layer approach transports feedback, dynamically via the layer margins to enable the remuneration for e.g. load, latency or other mismatch of requirements and resources by any deal with input to an additional layer. In the original OSI networking model, Layered communication approaches typically separate communication responsibilities into several layers, with a patent definition of the functionality of each layer. Cross layer optimization removes such strict restrictions to permit communication between layers to restore information and enable interfaces. For example, having knowledge of the existing physical condition will help a channel distribution offer at the MAC level in optimizing tradeoffs and achieve throughput maximization. The paper "A Cross Layer Design for Performance Enhancement in LTE-A Systems" consists of four steps: i) Analyze the various Optimization Techniques ii) Parameters Abstraction iii) Cross Layer Optimization iv) Performance Evaluation.

关键词： Automatic Repeat Request Long Term Evolution advanced

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MATRIX-vECTOR MULTIPLICATION USING POLARIZATION ROTATORS.

MATRIX-VECTOR MULTIPLICATION USING POLARIZATION ROTATORS.

引用

Topical Meeting on Optical Computing, Summaries of Papers Presented. Technical Digest Series v 11.

作者： Scharf, L. Cathey, W.T. Johnson, K.M. Univ of Colorado Boulder Boulder CO USA Univ of Colorado Boulder Boulder CO USA

ISBN: (纸本)0936659661

The potential application of optical systems to perform high speed, low cost signal processing with large parallelism has attracted the attention of researchers for many years. General optical processors have been developed that compute matrix-vector multiplications and other linear algebraic operations using incoherent light. One example is the Optical Matrix-vector Multiplier (OMvM), which calculates the discrete operation of a matrix-vector product, rather than the continuous correlation and convolution more commonly associated with optical processing. The goal of our research is to achieve 100 multiplied by 100 matrix-matrix multiplications in a microsecond, with 10 bit or greater accuracy. To achieve this goal, a new approach is needed. We describe a two-dimensional optical systolic processor with new algorithms, architectures, and devices which we believe will result in the evolution of an optical processor capable of meeting this goal. We outline our design principles for high-speed, high precision optical implementations of linear algebraic computations.

关键词： OPTICAL DATA processing

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Parallel architectures for computing the Hough transform and CT image reconstruction

Parallel architectures for computing the Hough transform and...

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Proceedings of the 1994 International Conference on Application Specific Array Processors

作者： Lin, L. Jain, v.K. Univ of South Florida Tampa United States

This paper discusses high-speed array implementations of two image processing algorithms, namely the 'Hough transform for Detection of line segments', and 'Backprojection in CT image reconstruction'. A multi-chip-module (MCM) construction is proposed consisting of three types of chips, a high speed multi-function nonlinear chip, a flexible Multiply-Accumulate chip, and an image kernel chip. Called v-array, it can be configured to have eight HOUGH modules, so as to produce the Hough transform of a 1024 × 1024 image in an estimated 13 ms in 2.0 micron CMOS technology (6.6 ms in 1.0 micron CMOS technology). Similarly, a v-array MCM can accommodate eight CT modules, which can produce the backprojected image in 209 ms in 2.0 micron CMOS technology (105 ms in 1.0 micron CMOS technology). To gain a significant speed advantage, we have developed an advanced multi-function cell for performing any one of four nonlinear operations: (1) square-root, (2) reciprocal, (3) sine/cosine, and (4) arctangent - - all realized in a single chip, accessible on a selectable basis. A 16 bit four-function 'one cycle' vLSI chip, fabricated in 2.0 micron CMOS technology, is presently available which outputs a new result every clock cycle. Using this nonlinear cell and two other cells, an application level Hough transform module and a CT module are presented.

关键词： Parallel processing systems

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Efficient Architecture for a High Performance Authenticated Encryption Algorithm on Reconfigurable Computing 9th

Efficient Architecture for a High Performance Authenticate...

引用

9th EAI International Conference on Advancement of Science and Technology, ICAST 2021

作者： Abebe, Abiy Tadesse Shiferaw, Yalemzewd Negash Kumar, P. G. v. Suresh School of Electrical and Computer Engineering Addis Ababa Institute of Technology AAU Addis Ababa Ethiopia Ambo University Ambo Ethiopia

ISBN: (纸本)9783030937089

High performance authenticated encryption algorithms are indispensable and preferable for securing the contemporary high speed wireless networks as they can perform their tasks without affecting overall performance of the network, and can provide data confidentiality, data integrity, and authentication cryptographic services simultaneously. Most of existing FPGA based architectures that have been proposed to enhance performance of such algorithms considered generic FPGA fabrics for implementations. Implementing complex algorithms using only traditional FPGA logic requires large amount of such resources that in turn can affect performance. In this work, an efficient architecture for AEGIS-128 authenticated encryption algorithm is proposed using both FPGAs’ embedded hard-cores such as digital signal processing slices and block random access memories that have not been fully exploited for such applications with balanced amount of generic logic. The aim is to reduce performance bottlenecks and enhance performance of AEGIS-128. The implementation results show that the proposed architecture outperforms existing similar approaches found in the literature in terms of throughput, and utilization of reduced amount of resources. © 2022, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： Cryptography

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Adaptive Lanczos methods for recursive condition estimation

Adaptive Lanczos methods for recursive condition estimation

引用

advanced signal-processing algorithms, architectures, and implementations

作者： Ferng, William R. Golub, Gene H. Plemmons, Robert J. NC State Univ Raleigh United States

Estimates for the condition number of a matrix are useful in many areas of scientific computing, including: recursive least squares computations, optimization, eigenanalysis, and general nonlinear problems solved by linearization techniques where matrix modification techniques are used. The purpose of this paper is to propose an adaptive Lanczos estimator scheme, which we call ale, for tracking the condition number of the modified matrix over time. Applications to recursive least squares (RLS) computations using the covariance method with sliding data windows are considered. ale is fast for relatively small n - parameter problems arising in RLS methods in control and signal processing, and is adaptive over time, i.e., estimates at time t are used to produce estimates at time t + 1. Comparisons are made with other adaptive and non-adaptive condition estimators for recursive least squares problems. Numerical experiments are reported indicating that ale yields a very accurate recursive condition estimator.

关键词： signal processing

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An optimal adder-based hardware architecture for the DCT/SA-DCT

An optimal adder-based hardware architecture for the DCT/SA-...

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Conference on visual Communications and Image processing 2005

作者： Kinane, A Muresan, v O'Connor, N Dublin City Univ Ctr Digital Video Proc Dublin Ireland

ISBN: (纸本)0819459763

The explosive growth of the mobile multimedia industry has accentuated the need for efficient vLSI implementations of the associated computationally demanding signal processing algorithms. This need becomes greater as end-users demand increasingly enhanced features and more advanced underpinning video analysis. One such feature is object-based video processing as supported by MPEG-4 core profile, which allows content-based interactivity. MPEG-4 has many computationally demanding underlying algorithms, an example of which is the Shape Adaptive Discrete Cosine Transform (SA-DCT). The dynamic nature of the SA-DCT processing steps pose significant vLSI implementation challenges and many of the previously proposed approaches use area and power consumptive multipliers. Most also ignore the subtleties of the packing steps and manipulation of the shape information. We propose a new multiplier-less serial datapath based solely on adders and multiplexers to improve area and power. The adder cost is minimised by employing resource re-use methods. The number of (physical) adders used has been derived using a common sub-expression elimination algorithm. Additional energy efficiency is factored into the design by employing guarded evaluation and local clock gating. Our design implements the SA-DCT packing with minimal switching using efficient addressing logic with a transpose memory RAM. The entire design has been synthesized using TSMC 0.09 mu m TCBN90LP technology yielding a gate count of 12028 for the datapath and its control logic.

关键词： DCT SA-DCT MPEG-4 ACE profile object coding vLSI low power hardware acceleration

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