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Design and implementation of viterbi decoder with FPGAs

JOURNAL OF vLSI signal processing SYSTEMS FOR signal IMAGE AND vIDEO TECHNOLOGY 1999年第1期21卷 5-14页

作者： Kivioja, M Isoaho, J vänskä, L Tampere Univ Technol Digital Media Inst FIN-33101 Tampere Finland Royal Inst Technol Dept Elect SE-16440 Kista Sweden Nokia Res Ctr FIN-00211 Helsinki Finland

In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. viterbi decoder, constraint length seven, was designed and simulated with vHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.

关键词： signal encoding

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A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection 25

A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hard...

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25th Euromicro Conference on Digital System Design (DSD)

作者： Herrmann, viktor Knapheide, Justin Steinert, Fritjof Stabernack, Benno Fraunhofer Inst Telecommun Heinrich Hertz Inst Berlin Germany Univ Potsdam Embedded Syst Architectures Signal Proc Potsdam Germany

ISBN: (纸本)9781665474047

With the recent advances in the fields of machine learning, neural networks and deep-learning algorithms have become a prevalent subject of computer vision. Especially for tasks like object classification and detection Convolutional Neuronal Networks (CNNs) have surpassed the previous traditional approaches. In addition to these applications, CNNs can recently also be found in other applications. For example the parametrization of video encoding algorithms as used in our example is quite a new application domain. Especially CNN's high recognition rate makes them particularly suitable for finding Regions of Interest (ROIs) in video sequences, which can be used for adapting the data rate of the compressed video stream accordingly. On the downside, these CNN require an immense amount of processing power and memory bandwidth. Object detection networks such as You Only Look Once (YOLO) try to balance processing speed and accuracy but still rely on power-hungry GPUs to meet real-time requirements. Specialized hardware like Field Programmable Gate Array (FPGA) implementations proved to strongly reduce this problem while still providing sufficient computational power. In this paper we propose a flexible architecture for object detection hardware acceleration based on the YOLO v3-tiny model. The reconfigurable accelerator comprises a high throughput convolution engine, custom blocks for all additional CNN operations and a programmable control unit to manage on-chip execution. The model can be deployed without significant changes based on 32-bit floating point values and without further methods that would reduce the model accuracy. Experimental results show a high capability of the design to accelerate the object detection task with a processing time of 27.5 ms per frame. It is thus real-time-capable for 30 FPS applications at frequency of 200 MHz.

关键词： FPGA Object Detection Hardware YOLO

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The priority curve algorithm for video summarization

The priority curve algorithm for video summarization

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MMDB 2004: Proceedings of the Second ACM International Workshop on Multimedia Databases

作者： Fayzullin, M. Subrahmanian, v.S. Albanese, M. Picariello, A. University of Maryland United States Università di Napoli Italy

ISBN: (纸本)1581139756

In this paper, we introduce the concept of a priority curve associated with a video. We then provide an algorithm that can use the priority curve to create a summary (of a desired length) of any video. The summary thus created exhibits nice continuity properties and also avoids repetition. We have implemented the priority curve algorithm (PCA) and compared it with other summarization algorithms in the literature. We show that PCA is faster than existing algorithms and also produces better quality summaries. The quality of summaries was evaluated by a group of 200 students in Naples, Italy, who watched soccer videos. We also briefly describe a soccer video summarization system we have built on using the PCA architecture and various (classical) image processing algorithms. Copyright 2004 ACM.

关键词： video signal processing

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Low Power Divider Using vedic Mathematics 3

Low Power Divider Using Vedic Mathematics

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3rd International Conference on Advances in Computing, Communications and Informatics (ICACCI)

作者： Kishor, Dalal Rutwik Bhaaskaran, v. S. Kanchana VIT Chennai Sch Elect & Commun Chennai Tamil Nadu India

ISBN: (纸本)9781479930807

Divider is an inevitable and basic hardware module employed in advanced and high speed digital signal processing (DSP) units of high precision. It is widely used in radar technology, communication, industrial control systems and linear predictive coding (LPC) algorithms in speech processing. This paper proposes a fast, low power and cost effective architecture of a divider using the ancient Indian vedic division algorithm. The merits of the proposed architecture are proved by comparing the gate count, power consumption and delay against the conventional divider architectures. The validation of the proposed architecture has resulted in 52.93 percent reduction in power dissipation against comparison with conventional divider using repeated subtraction. The designs were implemented using industry standard Cadence (R) software using 45nm technology library. The design has been validated on FPGA Spartan-3E kit. The validation results show appreciable reduction in circuit latency and in Look-Up-Table (LUT) utilization using proposed vedic divider than the conventional divider.

关键词： vedic divider Divider Circuit Arithmetic Circuits Division by Subtraction

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PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, vOLUME 154: REAL-TIME signal processing, 1978.

Proceedings of the Society of Photo-Optical Instrumentation ...

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Proceedings of the Society of Photo-Optical Instrumentation Engineers 1978年 154卷

The proceedings include 28 papers, 27 of them are indexed separately. Topics covered include advanced techniques of real-time signal processing in various fields, such as space information systems, radar data processing, missile guidance underwater acoustic imaging, wideband integrated optics. Also hardware architectures and algorithms for real-time signal processing are considered. Several presentations are devoted to digital approaches and analog implementations of real-time signal processing.

关键词： signal processing

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Implementation of RNS and LNS based addition and subtraction units for cryptography

Implementation of RNS and LNS based addition and subtraction...

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International Conference on vLSI Systems, Architecture, Technology and Applications (vLSI-SATA)

作者： Ch. Satish Kumar A. Prathiba v S Kanchana Bhaskaran School of Electronics Engineering VIT University Chennai campus Chennai India

ISBN: (纸本)9781509000371

The need for fast data processing and reducing the power dissipation of digital signal processing(DSP) algorithms and Cryptographic algorithms have provoked the development of efficient hardware implementations of residue number system (RNS) and logarithmic number system(LNS) arithmetic. This paper describes the implementation of adder and subtractor units by using RNS and LNS arithmetic. Addition and subtraction units are major and basic operations in public key cryptographic algorithms like Elliptic Curve Cryptography (ECC). In cryptography the use of finite fields plays a major role which is time consuming, there is a need for fast and efficient implementations.

关键词： Simulation Cryptography Power dissipation Adders Dynamic range very large scale integration signal processing algorithms

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Hardware/software trade-offs for advanced 3G channel coding

Hardware/software trade-offs for advanced 3G channel coding

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Design, Automation and Test in Europe Conference and Exhibition

作者： H. Michel A. Worm M. Munch N. Wehn Institute of Microelectronic System Design University of Kaiserslautern Kaiserslautern Germany ASIC Design Laboratories Zaventem Belgium

ISBN: (纸本)0769514715

Third generation's wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G's systems. Numerous existing and emerging standards require flexible implementations ("software radio"). Thus efficient implementations of the performance-critical parts as Turbo decoding on programmable architectures are of great interest. Besides high-performance DSPs, application-customized RISC cores offer the required performance while still maintaining the aspired flexibility. This paper presents for the first time Turbo decoder implementations on customized RISC cores and compares the results with implementations on state-of-the-art vLIW DSPs. The results of our studies show that the Log-MAP performance is about 50% higher that on an ST120, a current vLIW architecture.

关键词： Hardware Channel coding Decoding Digital signal processing Reduced instruction set computing vLIW signal generators Wireless communication signal processing algorithms Software standards

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An Image processing Application: Design of vLSI based Bilateral Filter using Distance Matrix Method 2

An Image Processing Application: Design of VLSI based Bilate...

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2nd IEEE International Conference on advanced Technologies in Intelligent Control, Environment, Computing and Communication Engineering, ICATIECE 2022

作者： Saranya, C. vijayananth, M.v. Mouleeshwaran, S. Kaviyarasu, D. K.S.Rangasamy College of Technology Department of ECE Tiruchengode India

ISBN: (纸本)9781665493963

The entire design structure is being impacted by advancements in electronic technology, which is posing a number of challenges for digital systems. In the fields of communications, image processing, and multimedia, vLSI-based image filter architectures are essential. Numerous applications based on vLSI architecture experience problems with significant size components that result in a filter design error during the floating-point arithmetic stages. The increased complexity of the filter design's component list is the issue encountered in the vLSI architecture. Noise removal often involves using the image filtering technique. There is a greater need for performance-based hardware sorting algorithms for low power embedded real-Time image filtering applications. Noise often taints an image while being transmitted from one location to another. The purpose of the denoising technique is to reduce noise while keeping any potential signal features that may be significant. Compare to the prior method, the usage of multipliers can be reduced based on the techniques of distance matrix and hardware resource sharing. The speed of the proposed vLSI architecture for the bilateral filter can be faster than the existing approach. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Design and Implementation of viterbi Decoder with FPGAs

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Journal of vLSI signal processing systems for signal, image and video technology 1999年第1期21卷 5-14页

作者： Kivioja, M. Isoaho, J. vänskä, L. Digital Media Institute Tampere University of Technology Tampere Finland Electronic System Design Department of Electronics The Royal Institute of Technology Kista Sweden Nokia Research Center Helsinki Finland

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Correctly rounded floating-point division for DSP-enabled FPGAs

Correctly rounded floating-point division for DSP-enabled FP...

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International Conference on Field Programmable Logic and Applications

作者： Bogdan Pasca Altera European Technology Centre High Wycombe UK

Floating-point division is a very costly operation in FPGA designs. High-frequency implementations of the classic digit-recurrence algorithms for division have long latencies (of the order of the number fraction bits) and consume large amounts of logic. Additionally, these implementations require important routing resources, making timing closure difficult in complete designs. In this paper we present two multiplier-based architectures for division which make efficient use of the DSP resources in recent Altera FPGAs. By balancing resource usage between logic, memory and DSP blocks, the presented architectures maintain high frequencies is full designs. Additionally, compared to classical algorithms, the proposed architectures have significantly lower latencies. The architectures target faithfully rounded results, similar to most elementary functions implementations for FPGAs but can also be transformed into correctly rounded architectures with a small overhead. The presented architectures are built using the Altera DSP Builder advanced framework and will be part of the default blockset.

关键词： Digital signal processing Polynomials Field programmable gate arrays Approximation error Memory management

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