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检索条件"任意字段=Advanced Signal Processing: Algorithms, Architectures, and Implementations V"

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Straightforward implementation of DSP algorithms on systolic arrays

Straightforward implementation of DSP algorithms on systolic...

引用

CompEuro

作者： C. Bagaini A. Balboni C. Binda M. Porta v. Rampa D. Sciuto CEFRIEL Milano Italy Italtel SIT Milanese Italy CSTS-CNR Milano Italy Università di Brescia Brescia Italy

The status of the work on a high-level synthesis framework able to automatically generate an optimal architecture that implements a generic digital signal processing (DSP) algorithm is reported. Defining class-oriented architectural synthesis environments seems to be the key point for an efficient silicon compilation. The synthesis system is limited only to DSP algorithms defined in local recursive form, but, in the future, it will be extended to different architectures.< >

关键词： Digital signal processing Systolic arrays signal processing algorithms Gas discharge devices signal synthesis Resource management Logic design Layout Switches High level synthesis

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New algorithms and vLSI architectures for SRT division and square root

New algorithms and VLSI architectures for SRT division and s...

引用

Computer Arithmetic (ARITH)

作者： S.E. McQuillan J.v. McCanny R. Hamill Department of Electrical and Electronic Engineering The Institute of Advanced Microelectronics Queen''s University Belfast Belfast UK

Radix two algorithms for SRT division and square-rooting are developed. For these schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. vLSI array architectures for implementing the new division and square-rooting methods are also presented.< >

关键词： very large scale integration signal processing algorithms Arithmetic Algorithm design and analysis Digital signal processing Concurrent computing Microelectronics Power engineering and energy Computer architecture Frequency conversion

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Parallel architectures for real-time control

Parallel architectures for real-time control

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IEE Colloquium on High Performance Applications of Parallel architectures

作者： M.O. Tokhi M.A. Hossain M.J. Baxter P.J. Fleming Department of Automatic Control and Systems Engineering University of Sheffield Sheffield UK

The authors present an investigation into the utilisation of parallel computing techinques for real-time simulation and control of a flexible beam structure in transverse vibration. The performance demands of modern control systems require the employment of complex algorithms with demanding operations which, in turn, leads to shorter sampling times. Therefore, real-time performance in control applications where the use of advanced control methods is warranted becomes difficult to accomplish. Many demanding complex control processes cannot be satisfactorily realised with conventional uni-processor and multi-processor systems. Previous investigations have demonstrated the limitations of employing only transputers for real-time implementations in control applications. Alternative strategies where multi-processor based systems are employed, utilising digital signal processing (DSP) and parallel processing techniques, could provide suitable methodologies.< >

关键词： Digital control Simulation Parallel architectures Real time systems signal processing Structural engineering Computer aided engineering

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An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders

An implementation friendly low complexity multiplierless LLR...

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IEEE Workshop on signal processing Systems (SIPS)

作者： Min Li David Novo Bruno Bougard Frederik Naessens Liesbet van Der Perre Francky Catthoor Nomadic Embedded System Division IMEC Leuven Belgium ESAT K.U. Leuven Leuven Belgium

When combined with advanced FEC techniques such as the turbo code and LDPC code, soft-output MIMO sphere decoders significantly outperform hard-output sphere decoders. Hence, algorithms and implementations of soft-output sphere decoders have attracted intensive interest in recent years. Practical soft-output sphere decoder implementations often consist of a list generator and a LLR generator. Most existing implementations focus on the list generator, and the LLR generator is implemented in a relatively straightforward way. However, the LLR generator accounts for a great part of the complexity. Our contribution is an implementation friendly low complexity multiplierless LLR generator. We apply selective and incremental updating, algebraic simplifications and strength reductions to reduce the algorithmic complexity and to eliminate all multiplications. When integrated with the SSFE list generator, our scheme not only remove 100% multiplications, but also remove 26% to 83% additions, 76% to 94% bit-shifts and 63% to 91% memory operations. Besides the algorithmic aspects, we extract the key data-flow block with well-defined control signals. This can be easily mapped onto micro-architectures and implemented as the data-path in ASICs, or a function unit in ASIPs.

关键词： MIMO Decoding signal processing algorithms Parity check codes Detectors Turbo codes Application specific processors Forward error correction Baseband Embedded system

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SIMD vectorization of Non-Two-Power Sized FFTs

SIMD Vectorization of Non-Two-Power Sized FFTs

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International Conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Franz Franchetti Markus Puschel Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

SIMD (single instruction multiple data) vector instructions, such as Intel's SSE family, are available on most architectures, but are difficult to exploit for speed-up. In many cases, such as the fast Fourier transform (FFT), signal processing algorithms have to undergo major transformations to map efficiently. Using the Kronecker product formalism, we rigorously derive a novel variant of the general-radix Cooley-Tukey FFT that is structured to map efficiently for any vector length v and radix. Then, we include the new FFT into the program generator spiral to generate actual C implementations. Benchmarks on Intel's SSE show that the new algorithms perform better on practically all sizes than the best available libraries Intel's MKL and FFTW.

关键词： Flexible printed circuits Libraries Discrete Fourier transforms signal processing algorithms Computer architecture Spirals Fast Fourier transforms Automatic programming Embedded computing Computer aided instruction

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Custom versus standard architectures for implementing speech coding algorithms

Custom versus standard architectures for implementing speech...

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IEEE Pacific Rim Conference on Communications, Computers and signal processing

作者： P.D. Schuler R.H.S. Hardy v. Cuperman School of Engineering Science Simon Fraser University Burnaby BC Canada

An application-specific integrated circuit (ASIC) for implementing low-delay speech coding algorithms is presented. The architecture consists of two types of arithmetic units: a variable number of adaptive arithmetic units (AAUs) connected in parallel and one distortion arithmetic unit (DAU). Each AAU contains an adaptive datapath which allows the units to perform various operations, such as filtering and inter product calculations, with a minimum of hardware. The DAU simplifies the codebook search for vector quantization by computing and comparing distortion measurements. The number of AAUs is optimized for power consumption and chip area. One efficient configuration consists of four AAUs. This configuration implements the lattice low-delay vector excitation coding algorithm with an estimated power consumption of less than 300 mW and area of 90 mm/sup 2/, which compares favorably with implementations on general-purpose digital signal processing (DSP) chips.< >

关键词： Speech coding Arithmetic Application specific integrated circuits signal processing algorithms Energy consumption Digital signal processing chips Adaptive filters Filtering Hardware vector quantization

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Energy-Efficient Synthetic-Aperture Radar processing on a Manycore Architecture

Energy-Efficient Synthetic-Aperture Radar Processing on a Ma...

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International Conference on Parallel processing (ICPP)

作者： Zain-Ul-Abdin Anders Åhlander Bertil Svensson Centre for Research on Embedded Systems (CERES) Halmstad University Halmstad Sweden Saab AB Gothenburg Sweden

The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in real time. Many core architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner. In this paper, we evaluate a many core architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an auto focus criterion calculation and the fast factorized back-projection algorithm, both key components in modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the auto focus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized back projection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient.

关键词： signal processing algorithms Computer architecture Synthetic aperture radar Parallel processing Radar imaging Image resolution

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Bit-serial architectures for parameter extraction and phonetic encoding

Bit-serial architectures for parameter extraction and phonet...

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CompEuro

作者： E. Martinez P. Martinez v. Rodellar P. Gomez Dpto. de Arquitectura y Tecnología de Sistemas Informáticos Facultad de Informática Madrid Spain

One interesting application of digital signal processing is low-level speech recognition. A description is presented of the design of a whole structure made up of two substructures: an LPC (linear predictive coding) filter to compact the information present in the voice trace and a bit serial neural network which is used for the phonetic encoding of this trace. These substructures are designed with a silicon compiler adapted for digital signal algorithms and bit-serial architectures.< >

关键词： Parameter extraction Linear predictive coding Digital signal processing Speech recognition Information filtering Information filters Nonlinear filters Neural networks Encoding signal design

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E-discover State-of-the-art Research Trends of Deep Learning for Computer vision

E-discover State-of-the-art Research Trends of Deep Learning...

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IEEE International Conference on Systems, Man and Cybernetics (SMC)

作者： Li, Annie A. S. Trappey, Amy J. C. Trappey, Charles v. Fan, C. Y. Natl Tsing Hua Univ Dept Ind Engn & Engn Management Hsinchu Taiwan Natl Chiao Chiao Tung Tung Univ Dept Management Sci Hsinchu Taiwan Natl Appl Res Lab Sci & Technol Policy & Informat Ctr Taipei Taiwan

ISBN: (纸本)9781728145693

Computer vision (Cv) attempts to mimic human eyes for image processing and identifications of detailed visual information, such as object positions, features of appearances, and even human emotions and behaviors. In this research, more than one hundred literatures, relating to applying deep learning (DL) methodologies in advanced computer visions (2010 similar to 2018), are reviewed and analyzed. The objective is to discover the state-of-the-art DL methods, topics, and trends for Cv and their practical applications. DL algorithms aim at representing multilevels of distributed neural networks. Because of the enhancement of high speed computational power, DL modeling, based on accumulated big data analytics, has found practical applications for non-supervised intelligent decision supports, such as detection of product defects and prognosis of machine malfunctions based on real-time signal or feature data analyses. There are a vast number of literature, describing DL related researches, developments, and implementations for problem solving. For the comprehensive mining of the related literature, we integrate Latent Dirichlet Allocation (LDA), K-means (Clustering), and normalized term frequency-inverse document frequency (NTF-IDF) approaches to discover, or called technology mining, of the major trends in DL for computer visions, specifically for key applications in object detection, semantic segmentation, image retrieval, and human pose estimation.

关键词： deep learning latent dirichlet allocation k-means normalized term frequency-inverse document frequency

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Architectural synthesis of an image processing algorithm using IRIS

Architectural synthesis of an image processing algorithm usi...

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Workshop on vLSI signal processing

作者： D.W. Trainor R.F. Woods J.v. McCanny Institute of Advanced Microelectronics Queen''s University Belfast Belfast UK

Details are presented of the IRIS synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive vLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit.

关键词： Image processing Iris Hardware Circuit synthesis signal processing algorithms signal synthesis very large scale integration Digital signal processing Silicon Discrete cosine transforms

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