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Design, Automation and Test in Europe Conference and Exhibition

作者： A. Burg M. Borgmanr M. Wenk C. Studer H. Bolcskei Integrated Systems Laboratory ETH Zurich Zurich Switzerland Communication Technology Laboratory ETH Zurich Zurich Switzerland

ISBN: (纸本)9783981080100

We describe the vLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area. In particular, algorithms and vLSI architectures for sphere decoding (SD) and K-best detection are considered, and the corresponding trade-offs between uncoded error-rate performance, silicon area, and throughput are explored. We show that SD with a per-block run-time constraint is best suited for practical implementations

关键词： MIMO Wireless communication signal processing algorithms Detectors Throughput very large scale integration Silicon Receiving antennas Laboratories Maximum likelihood decoding

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A low power based partitioning and binding technique for single chip application specific DSP architectures

A low power based partitioning and binding technique for sin...

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IEEE International Conference on Innovative Systems in Silicon

作者： R.v. Cherabuddi M.A. Bayoumi The Center for Advanced Computer Studies University of Southwestern Louisiana Lafayette LA USA

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital signal processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given data flow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.

关键词： Digital signal processing chips High level synthesis signal synthesis Partitioning algorithms variable speed drives Communication switching Data flow computing Application software Computer architecture Minimization

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The real-time implementations of AMR codec for IMT-2000 system

The real-time implementations of AMR codec for IMT-2000 syst...

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International Conference on advanced Communication Technology (ICACT)

作者： Hyung-Jung Kim Deock-Gu Jee Man-Ho Park Byung-Sik Yoon Song-In Choi Mobile A/V Research Team Electronics and Telecommunications Research Institute (ETRI) South Korea Mobile A/V Research Team Electronics and Telecommunications Research Institute (ETRI)

We present the software and hardware implementations of AMR codec for IMT-2000 system. The real-time implementations of AMR codec algorithm are achieved using TMS320C62xx DSP chip and Teak-Lite DSP core. We describe respectively efficient software schemes for coding AMR codec algorithm and hardware designs. The AMR codec is evaluated and confirmed in 3GPP test sequences, stand-alone test system and ETRI IMT-2000 prototype system

关键词： Real time systems Digital signal processing chips Hardware Speech codecs Assembly System testing GSM Software algorithms Algorithm design and analysis Software prototyping

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A Novel DA-Based Parallel Architecture for Inner-Product of variable vectors

A Novel DA-Based Parallel Architecture for Inner-Product of ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Anil Kali Samrat L. Sabat Pramod K. Meher CASEST University of Hyderabad Hyderabad India Department of Computer Science & Engineering C. V. Raman Global University Bhubaneswar India

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Computation of the inner products is frequently used in machine learning (ML) algorithms apart from signal processing and communication applications. Distributed arithmetic (DA) has been frequently employed for area-time efficient inner-product implementations. In conventional DA-based architectures, one of the vectors is constant and known a priori. Hence, the traditional DA architectures are not suitable when both vectors are variable. However, computing the inner product of a pair of variable vectors is frequently used for matrix multiplication of various forms and convolutional neural networks. In this paper, we present a novel DA-based architecture for computing the inner product of variable vectors. To derive the proposed architecture, the inner product of any given length is decomposed into a set of short-length inner products, such that the inner product could be computed by successive accumulation of the results of short-length inner products. We have designed a DA-based architecture for the computation of the short-length inner-product of variable vectors and used that in successive clock cycles to compute the whole inner-product by successive accumulation. The post-layout synthesis results using Cadence Innovus with a GPDK 90nm technology library show that the proposed DA-based parallel architecture offers significant advantages in area-delay product and energy consumption over the bit-serial DA architecture.

关键词： Energy consumption Machine learning algorithms Architecture signal processing algorithms Machine learning signal processing vectors

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Gateway diversity for Q/v feeder links: Requirements, characteristics, and challenges

Gateway diversity for Q/V feeder links: Requirements, charac...

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advanced Satellite Mobile Systems (ASMS)

作者： Argyrios Kyrgiazos Barry Evans Centre for Communication Systems Research University of Surrey Guildford Surrey United Kingdom

In this paper, we review the work of the gateway diversity schemes for Q/v band feeder links for a future HTS system. As each gateway will carry very high capacity, it is essential to ensure very high availabilities for the feeder links, typically greater than 99.9%. In order to do so, spatial diversity is required, since Adaptive Coding and Modulation (ACM) and Uplink Power Control (UPC) are unable to cope with the fade dynamics encountered at these high frequency bands. In an effort to reduce the total number of gateways in the system and to result in a more cost effective system, the concept of Smart gateways has emerged. We first review different architectures implementations and highlight their similarities and differences. We then outline the technological challenges and the issues that the envisaged solutions should consider during the design process. Finally we give views on a technology roadmap to meet these challenges.

关键词： Logic gates Payloads Satellites Availability Switches Frequency division multiplexing

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Hardware Implementation Analysis of the MD5 Hash Algorithm

Hardware Implementation Analysis of the MD5 Hash Algorithm

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： K. Jarvinen M. Tommiska J. Skytta Signal Processing Laboratory Helsinki University of Technology Finland

Hardware implementation aspects of the MD5 hash algorithm are discussed in this paper. A general architecture for MD5 is proposed and several implementations are presented. An extensive study of effects of pipelining on delay, area requirements and throughput is performed, and finally certain architectures are recommended and compared to other published MD5 designs. The designs were implemented on a Xilinx virtex-II XC2v4000-6 FPGA and a throughput of 586 Mbps was achieved with logic requirements of only 647 slices and 2 BlockRAMs. Methods to increase the throughput to gigabit-level were also studied and an implementation of parallel MD5 blocks achieving a throughput of over 5.8 Gbps was introduced. At least to the authors' knowledge, MD5 designs presented in this paper are the fastest published FPGA-based architectures at the time of writing.

关键词： Hardware Algorithm design and analysis signal processing algorithms Throughput Field programmable gate arrays Acceleration Table lookup Logic design Logic devices signal design

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Quantifying the improvement in energy savings for LTE eNodeB baseband subsystem with technology scaling and multi-core architectures

Quantifying the improvement in energy savings for LTE eNodeB...

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National Conference on Communications (NCC)

作者： Hari Krishna Boyapati R v Rajakumar Saswat Chakrabarti G S S School of Telecommunications Indian Institute of Technology Kharagpur India Campus of IIITH Rajiv Gandhi University of Knowledge Technologies Hyderabad India

Recent wireless broadband cellular standards are aimed at making provisions for supporting very high data rate applications in limited available bandwidth. The most sophisticated as well as computationally complex subsystem of a transceiver of any such system is the baseband processing part of the system. A multi-core processor is typically needed to provide the required computational power for implementing the complex baseband processing subsystem such as that of LTE transceiver. The energy consumption in the baseband part of subsystem is a very significant component of the total energy expenditure of a cellular radio system, particularly when system employs MIMO and advanced vLSI state of art. This paper aims at reducing the energy consumption and also quantify the achievable energy savings by applying the recent trends in vLSI such as CMOS technology scaling and usage of new heterogeneous multi-core architectures specific to signal processing. To be able to explore and apply these energy efficient techniques, we have first estimated the energy consumption in LTE baseband functions then we have explored possible energy savings obtained from technology scaling and optimum heterogeneous combination of architectures for mapping baseband algorithms.

关键词： Baseband Power demand Digital signal processing Energy consumption Multicore processing 3G mobile communication

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Area and time efficient implementations of matrix multiplication on FPGAs

Area and time efficient implementations of matrix multiplica...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Ju-wook Jang Seonil Choi v.K.K. Prasanna Electronic Engineering Sogang University Seoul South Korea Electrical Engineering-Systems University of Southern California Los Angeles CA USA

We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the previous designs and our design are 14.45, 4.93, and 2.35, respectively, for 4 /spl times/ 4 matrix multiplication. The latency of one of the previous design is 0.57 /spl mu/s, while our design takes 0.15 /spl mu/s using 18% less area. The area of our designs is smaller by 11% - 46% compared with the best known systolic designs with the same latency for the matrices of sizes 3 /spl times/ 3 - 12 /spl times/ 12. The performance improvements tend to grow with the problem size.

关键词： Field programmable gate arrays Delay Frequency signal processing algorithms signal processing Hardware Kernel Graphics Robots Image processing

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Spatial evolutionary spectrum for DOA estimation and blind signal separation

Proceedings of SPIE - The International Society for Optical ...

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Proceedings of SPIE - The International Society for Optical Engineering 1999年 3807卷 480-490页

作者： Kayhan, A. Salim Amin, Moeness G.

In this paper, we use the concept of evolutionary spectrum to solve key problems in array processing. We present Cross-power Evolutionary Periodogram for direction finding and blind separation of nonstationary signals. We model nonstationary signals received by each sensor in the array as a sum of complex sinusoids with time-varying amplitudes. These amplitudes carry information about the direction of arrival which may also be time-varying. We first estimate the time-varying amplitudes, then use the results for the estimation of evolutionary cross-power distributions of the sensor data. Next, using cross-power estimates at time-frequency samples of interest, we estimate the directions of arrival using one of the existing high resolution direction finding methods. If the directions are time-varying, we select time-frequency points around the time of interest. By carrying out the estimation at different times, we obtain the directions as a function of time. If the sources are stationary, then we can use all time-frequency points of interest for the estimation of fixed directions. We also use whitening and subspace methods to find the mixing matrix and separate the signals received by the array. Simulation examples illustrating the performances of the proposed algorithms are presented.

关键词： Parallel processing systems

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Optimized Implementation of Modified Gram Schmidt Algorithm on vLIW Architecture

Optimized Implementation of Modified Gram Schmidt Algorithm ...

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World Conference on Complex Systems

作者： Mohamed Najoui Said Belkouch Anas Hatim Noureddine Chabini E2SN Lab ENSET-Rabat Mohamed V University Rabat Morocco LGEMS Lab ENSA-Agadir Ibn Zohr University Agadir Morocco LGECOS Lab ENSA-Marrakech Cadi Ayyad University Marrakech Morocco Royal Military College of Canada Kingston ON Canada

Modified Gram Schmidt (MGS) is one of the well-known forms of QR decomposition (QRD) algorithms. It has been used in many signal and image processing applications to solve least square problem, linear equations or to invert matrices. Nevertheless, QRD is considered a computationally expensive operation, and its sequential implementation doesn't meet the requirements of many real time applications. In this paper, we propose an optimized MGS algorithm version based on software pipelining and loop unrolling techniques. The suggested MGS version is parallel and well suited for vLIW architectures. The implementation is done under TI C6678 vLIW DSP and the obtained results show great improvements against the standard MGS and the optimized vendor QRD implementations.

关键词： vLIW Kernel signal processing algorithms Computer architecture Parallel processing Matrix decomposition Software algorithms

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