This paper describes a general purpose interconnection switch applicable to reconfigurable architectures. The switch has been used in the design of reconfigurable architectures and in processor arrays that require rec...
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This paper describes a general purpose interconnection switch applicable to reconfigurable architectures. The switch has been used in the design of reconfigurable architectures and in processor arrays that require reconfigurable interconnections. The reconfigurable switch has the desirable properties that it is both scalable and C-testable. Furthermore, the switch is shown to be C-configurable;that is, the number of configurations required to test a network of switches is independent of the size of the network. Criteria are given for selecting BIT techniques and implementations for reconfigurable architectures. algorithms are presented for generating configuration values and test data. Finally, the authors' BIT implementation is then presented and analyzed and is shown to provide 100% fault coverage for single S-A-O, S-A-1, bridging, and high impedance, permanent combinational faults.
In this paper we describe aspects of an ongoing program of work aimed at the practical realization of systolic array structures to implement digital adaptive beam-forming algorithms.
ISBN:
(纸本)0819406945
In this paper we describe aspects of an ongoing program of work aimed at the practical realization of systolic array structures to implement digital adaptive beam-forming algorithms.
This brief presents efficient single-rate architectures for the one-dimensional orthonormal discrete wavelet transform (DWT). This brief makes two contributions, First, we show that architectures that are based on the...
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This brief presents efficient single-rate architectures for the one-dimensional orthonormal discrete wavelet transform (DWT). This brief makes two contributions, First, we show that architectures that are based on the quadrature mirror filter (QMF) lattice structure require approximately half the number of multipliers and adders than corresponding direct-form structures. Second, we present techniques for mapping the 1-D orthonormal DWT to folded and digit-serial architectures which are based on the QMF lattice structure. For folded architectures, we discuss two techniques for mapping the QMF lattice structure to hardware. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques, The proposed folded and digit-serial QMF lattice structures are attractive choices for implementations of the orthonormal DWT which require low area and low power dissipation.
A new derivation of the QR-based fast recursive least squares algorithms for Toeplitz matrices is presented. algorithms for computing Q and R in the QR decomposition of the data matrix are proposed. These algorithms c...
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ISBN:
(纸本)0819406945
A new derivation of the QR-based fast recursive least squares algorithms for Toeplitz matrices is presented. algorithms for computing Q and R in the QR decomposition of the data matrix are proposed. These algorithms can be efficiently incorporated with the fast recursive least squares algorithm and can be performed only when they are needed.
Some recent results in the theory of adaptive array detection are presented. Detection curves are given for various detection algorithms. These detection algorithms are suitable for nulling out noise or interference s...
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ISBN:
(纸本)0819406945
Some recent results in the theory of adaptive array detection are presented. Detection curves are given for various detection algorithms. These detection algorithms are suitable for nulling out noise or interference sources in which the noise statistics are to be estimated from target- free data. They share the constant false alarm rate property, so that their false alarm rate can be set without knowledge of the noise covariance matrix. Also considered is a detection algorithm employing diagonal loading.
An arithmetic unit based on a high-speed multiplier with a redundant binary addition tree is proposed. It is efficient for numerical computations with iteration of multiplications and addition/subtractions. A new mult...
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ISBN:
(纸本)0819406945
An arithmetic unit based on a high-speed multiplier with a redundant binary addition tree is proposed. It is efficient for numerical computations with iteration of multiplications and addition/subtractions. A new multiplier recoding method makes the arithmetic unit efficient for these computations.
This paper explores novel techniques involving number theoretic concepts to perform real-time digital signalprocessing for high bandwidth data stream applications in digital signalprocessing. Often the arithmetic ma...
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ISBN:
(纸本)081940943X
This paper explores novel techniques involving number theoretic concepts to perform real-time digital signalprocessing for high bandwidth data stream applications in digital signalprocessing. Often the arithmetic manipulations are simple in form (cascades of additions and multiplications in a well defined structure) but the numbers of operations that have to be computed every second can be large. This paper discusses ways in which new number theoretic mapping techniques can be used to perform DSP operations by both reducing the amount of hardware involved in the circuitry and by allowing the construction of very benign architectures down to the individual cells. Such architectures can be used in aggressive VLSI/ULSI implementations. We restrict ourselves to the computation of linear filter and transform algorithms, with the inner product form, which probably account for the vast majority of digital signalprocessing functions implemented commercially.
Scheduling and retiming are important techniques used in the design of hardware and software implementations of digital signalprocessingalgorithms. In this paper, techniques are developed for generating all scheduli...
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Scheduling and retiming are important techniques used in the design of hardware and software implementations of digital signalprocessingalgorithms. In this paper, techniques are developed for generating all scheduling and retiming solutions for a strongly connected data-flow graph, allowing a designer to explore the space of possible implementations. Formulations are developed for two scheduling problems. The first scheduling problem assumes a bit-parallel target architecture. The formulation for this problem is general because it considers retiming the dataflow graph as part of scheduling, and this formulation reduces to the retiming formulation as a special case. The second scheduling problem assumes a bit-serial target architecture. Based on these formulations, the conditions for a legal scheduling solution are derived, and a systematic technique is presented for exhaustively generating all legal scheduling solutions for a strongly connected data-flow graph. Since retiming is a special case of scheduling, this systematic technique can also be used for exhaustively generating all legal retiming solutions. A technique is also developed for exhaustively generating only those bit-parallel schedules which satisfy a given set of resource constraints, The techniques for exhaustively generating scheduling and retiming solutions are demonstrated for several filters. For example, we show that a simple filter such as the biquad has 224 possible retiming solutions for a latency of one time unit. We also show that a fifth-order wave digital elliptic filter has 4.7 million and 580 million scheduling solutions for iteration periods of 17 and 18, respectively.
An iterative solution is given for solving deblurring problems having nonnegativity constraints through the use of methods motivated by tomographic imaging.
ISBN:
(纸本)0819404098
An iterative solution is given for solving deblurring problems having nonnegativity constraints through the use of methods motivated by tomographic imaging.
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