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Low power implementation of a turbo-decoder on programmable architectures

Low power implementation of a turbo-decoder on programmable ...

引用

Asia and South Pacific Design Automation Conference

作者： F. Gilbert A. Worm N. Wehn Institute of Microelectronic Systems Department of Electrical Engineering and Information Technology University of Kaiserslautern Germany

ISBN: (纸本)0780366336

Low power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on the system level by the use of an intelligent cancellation technique, and on the implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of turbo-decoders based on voltage scheduling for third generation wireless systems.

关键词： Dynamic voltage scaling Turbo codes Iterative decoding Processor scheduling Forward error correction signal processing algorithms Channel coding Error correction Redundancy Bit error rate

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Trends in design of massively parallel coprocessors implemented in digital ASICs

Trends in design of massively parallel coprocessors implemen...

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International Joint Conference on Neural Networks (IJCNN)

作者： P. Foldesy Analogic and Neural Computing Laboratory Computer and Automation Research Institute Hungarian Academy of Sciences (ATOMKI) Budapest Hungary

This paper collects the most recent parallel coprocessors and highlights the recent trends. It is shown that the single chip massively parallel processor implementations seem to disappear from the scientific investigations (with the exception of low-level near-sensor image processing). Meanwhile, the formerly developed architectures have moved inside complex system-on-chips/microprocessors. The common aspect of the recent architectures is the advanced processing element and internal interconnection solutions, and the dominant mid-grain parallelism (i.e. up to a hundred processing element per chip).

关键词： Coprocessors Application specific integrated circuits Concurrent computing Parallel processing Systolic arrays Radar signal processing signal processing algorithms Laboratories Automation Image processing

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A pipelined multi-softcore approach for the HOG algorithm

A pipelined multi-softcore approach for the HOG algorithm

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Conference on Design and architectures for signal and Image processing

作者： José Arnaldo Mascagni de Holanda João Manuel Paiva Cardoso Eduardo Marques Federal Institute of São Paulo Brazil Universidade do Porto Porto Porto PT University of Sao Paulo S??o Carlos Brazil

ISBN: (纸本)9781509030859

This paper describes the mapping and the acceleration of an object detection algorithm on a multiprocessor system based on an FPGA. We use HOG (Histogram of Oriented Gradients), one of the most popular algorithms for detection of different classes of objects and currently being used in smart embedded systems. The use of HOG on such systems requires efficient implementations in order to provide high performance possibly with low energy/power consumption budgets. Also, as variations and adaptations of this algorithm are needed to deal with different scenarios and classes of objects, programmability is required to allow greater development flexibility. In this paper we show our approach towards implementing the HOG algorithm into a multi-softcore Nios ii based-system, bearing in mind high-performance and programmability issues. By applying source-to-source transformations we obtain speedups of 19× and by using pipelined processing we reduce the algorithms execution time 49×. We also show that improving the hardware with acceleration units can result in speedups of 72.4× compared to the embedded baseline application.

关键词： Histograms Support vector machines Parallel processing Field programmable gate arrays Program processors Object detection Hardware

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Systematic architecture exploration for implementing interference suppression techniques in wireless receivers

Systematic architecture exploration for implementing interfe...

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IEEE Workshop on signal processing Systems (SIPS)

作者： Ning Zhang B. Haller R. Brodersen Wireless Research Laboratory Lucent Technologies Inc. USA Berkeley Wireless Research Center Department of EECS University of California Berkeley USA

Future wireless systems are required to provide higher data rates, improved spectral efficiency and greater capacity. This can be achieved at the cost of increased signal processing complexity. The successful implementation of advanced algorithms and dedicated hardware architectures to tackle the demanding signal processing tasks calls for an integrated development process. It must effectively exploit the many interrelations between the different levels of the design hierarchy and efficiently bridge the gap between system concepts and their VLSI circuit realization. This paper presents the algorithm and architecture level design of interference suppression techniques for advanced wireless receivers based on the use of multiple antenna elements in combination with appropriate signal combining. A systematic approach to architecture exploration is demonstrated which leads to efficient implementations in terms of both power consumption and silicon area.

关键词： signal processing algorithms Costs Hardware Bridge circuits Very large scale integration signal design Algorithm design and analysis Interference suppression Receiving antennas Energy consumption

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Nonlinear biomedical signal processing /

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2000年

作者： edited by Metin Akay.

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Analysis of myocardial texture in resting echocardiographic images predicts recovery one year after myocardial infarction

Analysis of myocardial texture in resting echocardiographic ...

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IEEE signal processing algorithms, architectures, Arrangements, and Applications Conference

作者： M. Strzelecki S. Skonieczka J. D. Kasprzak M. Simiera B. W. Michalski P. Lipiec Institute of Electronics Technical University of Lodz Lodz Poland II Chair and Dept. of Cardiology Medical University of Lodz Lodz Poland

ISBN: (纸本)9781509026616

The aim of this research is to develop a method for prediction of left ventricular recovery one year after myocardial infarction using texture parameters estimated for static ultrasound images. The study is performed for the monochrome and color (contrast based) echocardiograms that allow advanced evaluation of myocardial function. The analysis includes investigation of different texture feature selection methods and application of multilayer neural network, Support Vector Machine, and decision tree based Adaboost algorithm for recovery prediction. The obtained preliminary results are promising;estimated prediction error is lower than 30% for all used prediction tools.

关键词： Myocardium Support vector machines Decision trees Heart Ultrasonic imaging Image color analysis Imaging Ultrasonography Decision Trees Myocardium image colour analysis Support Vector Network Myocardial Infarction Heart Imaging Error of prediction texture Color Contrast

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Parallel architectures for real-time control

Parallel architectures for real-time control

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IEE Colloquium on High Performance Applications of Parallel architectures

作者： M.O. Tokhi M.A. Hossain M.J. Baxter P.J. Fleming Department of Automatic Control and Systems Engineering University of Sheffield Sheffield UK

The authors present an investigation into the utilisation of parallel computing techinques for real-time simulation and control of a flexible beam structure in transverse vibration. The performance demands of modern control systems require the employment of complex algorithms with demanding operations which, in turn, leads to shorter sampling times. Therefore, real-time performance in control applications where the use of advanced control methods is warranted becomes difficult to accomplish. Many demanding complex control processes cannot be satisfactorily realised with conventional uni-processor and multi-processor systems. Previous investigations have demonstrated the limitations of employing only transputers for real-time implementations in control applications. Alternative strategies where multi-processor based systems are employed, utilising digital signal processing (DSP) and parallel processing techniques, could provide suitable methodologies.< >

关键词： Digital control Simulation Parallel architectures Real time systems signal processing Structural engineering Computer aided engineering

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Toward the synthesis of fixed-point code for matrix inversion based on Cholesky decomposition

Toward the synthesis of fixed-point code for matrix inversio...

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Conference on Design and architectures for signal and Image processing

作者： Matthieu Martel Amine Najahi Guillaume Revy LIRMM Univ. Montpellier II Montpellier France DALI Univ. Perpignan Via Domitia Perpignan France CNRS LIRMM Montpellier France

Matrix inversion is a computationally intensive basic block of many digital signal processing algorithms. To decrease the cost of their implementations, programmers often prefer the fixed-point arithmetic. This arithmetic requires less resources and runs faster than the floating-point arithmetic, but all the arithmetical details must be handled by the programmer. In this article, we overcome this drawback by presenting an automated approach to synthesize fixed-point code for matrix inversion based on Cholesky decomposition. First we rigorously define the square root and division operators especially in terms of rounding error, and we implement them in the CGPE library. This allows us to provide accuracy certificates for the generated code. Second we propose a workflow based on Cholesky decomposition that carefully uses these operators to produce accurate code for the basic blocks of matrix inversion. Finally we illustrate the efficiency of our approach on some benchmarks, and show how it allows us to synthesize accurate code in a few seconds and thus to reduce the development time of fixed-point matrix inversion.

关键词： Matrix decomposition Accuracy Digital signal processing Symmetric matrices Algorithm design and analysis

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An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders

An implementation friendly low complexity multiplierless LLR...

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IEEE Workshop on signal processing Systems (SIPS)

作者： Min Li David Novo Bruno Bougard Frederik Naessens Liesbet Van Der Perre Francky Catthoor Nomadic Embedded System Division IMEC Leuven Belgium ESAT K.U. Leuven Leuven Belgium

When combined with advanced FEC techniques such as the turbo code and LDPC code, soft-output MIMO sphere decoders significantly outperform hard-output sphere decoders. Hence, algorithms and implementations of soft-output sphere decoders have attracted intensive interest in recent years. Practical soft-output sphere decoder implementations often consist of a list generator and a LLR generator. Most existing implementations focus on the list generator, and the LLR generator is implemented in a relatively straightforward way. However, the LLR generator accounts for a great part of the complexity. Our contribution is an implementation friendly low complexity multiplierless LLR generator. We apply selective and incremental updating, algebraic simplifications and strength reductions to reduce the algorithmic complexity and to eliminate all multiplications. When integrated with the SSFE list generator, our scheme not only remove 100% multiplications, but also remove 26% to 83% additions, 76% to 94% bit-shifts and 63% to 91% memory operations. Besides the algorithmic aspects, we extract the key data-flow block with well-defined control signals. This can be easily mapped onto micro-architectures and implemented as the data-path in ASICs, or a function unit in ASIPs.

关键词： MIMO Decoding signal processing algorithms Parity check codes Detectors Turbo codes Application specific processors Forward error correction Baseband Embedded system

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Energy-Efficient Synthetic-Aperture Radar processing on a Manycore Architecture

Energy-Efficient Synthetic-Aperture Radar Processing on a Ma...

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International Conference on Parallel processing (ICPP)

作者： Zain-Ul-Abdin Anders Åhlander Bertil Svensson Centre for Research on Embedded Systems (CERES) Halmstad University Halmstad Sweden Saab AB Gothenburg Sweden

The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in real time. Many core architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner. In this paper, we evaluate a many core architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an auto focus criterion calculation and the fast factorized back-projection algorithm, both key components in modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the auto focus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized back projection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient.

关键词： signal processing algorithms Computer architecture Synthetic aperture radar Parallel processing Radar imaging Image resolution

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