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作者： Michael A. Balog, iii Drexel University

学位级别：博士

Over the past few years FPGA hardware has become a logical choice for imple- menting cutting-edge signal processing applications. While there have been advances in FPGA technology, the common process of creating specialized hardware imple- mentations for them is a manual one involving extensive design exploration. Design exploration is a process that requires a designer to look for designs that t a set of performance characteristics such as size, throughput, or power depending on the application and it can be the most time consuming step when creating FPGA hard- ware. This process is a nontrivial task that requires extensive background knowledge of both FPGA hardware and the application being implemented. While advances have been made in automating the process of design, there is still a gap between the application writers and hardware engineers that can be lled. This thesis presents a novel approach for automating the generation of hardware design search spaces that contain a comprehensive set of ways to implement signal processing algorithms with FPGAs. To accomplish this we generate a set of equiv- alent mathematical representations for an input equation via a novel declarative programming language that avoids a number of diculties associated with the im- perative languages used by previous approaches. We show that this equation space is bounded in terms of bracketing and ordering of mathematical operations, and that by changing the way an equation is written we can generate unique hardware instantiations (designs). The generated instantiations are mapped to heterogeneous computing architectures and written in a structural hardware descriptive language style to ensure that the intended instantiation will behave as predicted in hardware. A software system was created based on this approach that generates an equation space for varying numbers of summed multiplications and converts each representa- tion into a comprehensive hardware design search space that can be a

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Redundant finite rings for fault-tolerant signal processors

Redundant finite rings for fault-tolerant signal processors

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advanced signal processing: algorithms, architectures, and implementations V

作者： Jullien, Graham A. Bizzan, S.S. Wigley, N.M. Miller, W.C. Univ. of Windsor Windsor ON Can

ISBN: (纸本)0819416207

Redundant Residue Number Systems (RRNS) have been proposed as suitable candidates for fault tolerance in compute intensive applications. The redundancy is based on multiple projections to moduli sub-sets and conducting a search for results that lie in a so-called illegitimate range. This paper presents RRNS fault tolerant procedures for a recently introduced finite polynomial ring mapping procedure (modulus replication RNS). The mapping technique dispenses with the need for many relatively prime ring moduli, which is a major draw-back with conventional RRNS systems. Although double, triple, and quadrupole modular redundancy can be implemented in the polynomial mapping structure, polynomial coefficient circuitry, or the independent direct product ring computational channels, for error detection and/or correction, this paper discusses the implementation of redundant rings which are generated by (1) redundant residues, (2) spare general computational channels, or (3) a combination of the two. The first architecture is suitable for RNS embedding in the MRRNS, and the second for single moduli mappings. The combination architecture allows a trade-off between the two extremes. The application area is in fault tolerant compute intensive DSP arrays.

关键词： Fault tolerant computer systems

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Time-varying higher order spectra

Time-varying higher order spectra

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advanced signal processing algorithms, architectures, and implementations II

作者： Boashash, Boualem O'Shea, Peter Queensland Univ. of Technology Brisbane Queensland Australia

ISBN: (纸本)0819406945

A general solution for the problem of time-frequency signal representation of nonlinear FM signals is provided, based on a generalization of the Wigner-Ville distribution. The Wigner-Ville distribution (WVD) is a second order time-frequency representation. That is, it is able to give ideal energy concentration for quadratic phase signals and its ensemble average is a second order time-varying spectrum. The same holds for Cohen's class of time-frequency distributions, which are smoothed versions of the WVD. The WVD may be extended so as to achieve ideal energy concentration for higher order phase laws, and such that the expectation is a time-varying higher order spectrum. The usefulness of these generalized Wigner-Ville distributions (GWVD) is twofold. Firstly, because they achieve ideal energy concentration for polynomial phase signals, they may be used for optimal instantaneous frequency estimation. Second, they are useful for discriminating between nonstationary processes of differing higher order moments. In the same way that the WVD is generalized, we generalize Cohen's class of TFDs by defining a class of generalized time-frequency distributions (GTFDs) obtained by a two dimensional smoothing of the GWVD. Another results derived from this approach is a method based on higher order spectra which allows the separation of cross-terms and auto- terms in the WVD.

关键词： signal Theory

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Adaptive Lanczos methods for recursive condition estimation

Adaptive Lanczos methods for recursive condition estimation

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advanced signal-processing algorithms, architectures, and implementations

作者： Ferng, William R. Golub, Gene H. Plemmons, Robert J. NC State Univ Raleigh United States

Estimates for the condition number of a matrix are useful in many areas of scientific computing, including: recursive least squares computations, optimization, eigenanalysis, and general nonlinear problems solved by linearization techniques where matrix modification techniques are used. The purpose of this paper is to propose an adaptive Lanczos estimator scheme, which we call ale, for tracking the condition number of the modified matrix over time. Applications to recursive least squares (RLS) computations using the covariance method with sliding data windows are considered. ale is fast for relatively small n - parameter problems arising in RLS methods in control and signal processing, and is adaptive over time, i.e., estimates at time t are used to produce estimates at time t + 1. Comparisons are made with other adaptive and non-adaptive condition estimators for recursive least squares problems. Numerical experiments are reported indicating that ale yields a very accurate recursive condition estimator.

关键词： signal processing

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Application of algorithm-based fault tolerance to high-level synthesis of signal flow graphs

Application of algorithm-based fault tolerance to high-level...

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advanced signal processing: algorithms, architectures, and implementations V

作者： Karnik, Tanay Ramaswamy, Shankar Kang, Steve M. Banerjee, Prithviraj Univ. of Illinois/Urbana-Champaign Urbana IL USA

ISBN: (纸本)0819416207

Algorithm based fault tolerance techniques have been used for systolic processors and general purpose multiprocessors. In this paper, we have applied an algorithm based fault tolerance technique to high-level synthesis of signal flow graphs. The technique incorporates reliability into synthesized DSP filters. Given a signal Flow Graph representation for these filters, our schemes synthesize a reliable schedule for the operations in them and allocate functional units to the operations subject to hardware and reliability constraints. We impose reliability constraints to avoid compensating errors in fault detection. Our first scheme uses the well known duplicate and compare approach, while the second uses a novel linearity based checking approach used in algorithm based fault tolerance methods for matrix computations. The schemes have been implemented and results obtained by using them on sample signal flow graphs are presented. These results show the linearity based scheme to have a low time overhead. For example, this scheme takes about 10% extra time for the reliable synthesis of a 10th order IIR filter. Our proposed work extends previous work in the area in three directions: (1) use of linearity based checks, over duplication based checks, (2) handling cyclic flow graphs, over previous proposals for acyclic graphs, and (3) reliability constrained hardware mapping. Extensions of the schemes to nonlinear flow graphs is also proposed.

关键词： Fault tolerant computer systems

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Analysis of coarse parallel architectures for artificial neural processing

Analysis of coarse parallel architectures for artificial neu...

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IEEE Workshop on Neural Networks for signal processing

作者： K.S. Gugel J.C. Principe S. Venkumahanti M.A. Lynch Computational NeuroEngineering Laboratory University of Florida Gainesville FL USA

A methodology for comparing various neural architectures and implementations is illustrated. The methodology consists of writing the artificial neural network (ANN) equations in a summation form and the applying a tool termed algorithmic timing parameter decomposition (ATPD). ATPD decomposes an algorithm or set of equations into a computation time formula comprising basic system primitives. A particular architecture has a corresponding computational time formula. Similarly, the primitive elements are dependent on the actual hardware realization and thus will change with the processor used in the system. Computation times therefore can be estimated for different parallel architectures. Implementation of a multilayer perceptron is analyzed in several digital signal processor (DSP)-based parallel architectures.< >

关键词： Parallel architectures Computer architecture Artificial neural networks Equations signal processing algorithms Writing Timing Hardware Concurrent computing Multilayer perceptrons

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Hardware/software trade-offs for advanced 3G channel coding

Hardware/software trade-offs for advanced 3G channel coding

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Design, Automation and Test in Europe Conference and Exhibition

作者： H. Michel A. Worm M. Munch N. Wehn Institute of Microelectronic System Design University of Kaiserslautern Kaiserslautern Germany ASIC Design Laboratories Zaventem Belgium

ISBN: (纸本)0769514715

Third generation's wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G's systems. Numerous existing and emerging standards require flexible implementations ("software radio"). Thus efficient implementations of the performance-critical parts as Turbo decoding on programmable architectures are of great interest. Besides high-performance DSPs, application-customized RISC cores offer the required performance while still maintaining the aspired flexibility. This paper presents for the first time Turbo decoder implementations on customized RISC cores and compares the results with implementations on state-of-the-art VLIW DSPs. The results of our studies show that the Log-MAP performance is about 50% higher that on an ST120, a current VLIW architecture.

关键词： Hardware Channel coding Decoding Digital signal processing Reduced instruction set computing VLIW signal generators Wireless communication signal processing algorithms Software standards

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PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, VOLUME 154: REAL-TIME signal processing, 1978.

Proceedings of the Society of Photo-Optical Instrumentation ...

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Proceedings of the Society of Photo-Optical Instrumentation Engineers 1978年 154卷

The proceedings include 28 papers, 27 of them are indexed separately. Topics covered include advanced techniques of real-time signal processing in various fields, such as space information systems, radar data processing, missile guidance underwater acoustic imaging, wideband integrated optics. Also hardware architectures and algorithms for real-time signal processing are considered. Several presentations are devoted to digital approaches and analog implementations of real-time signal processing.

关键词： signal processing

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Correctly rounded floating-point division for DSP-enabled FPGAs

Correctly rounded floating-point division for DSP-enabled FP...

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International Conference on Field Programmable Logic and Applications

作者： Bogdan Pasca Altera European Technology Centre High Wycombe UK

Floating-point division is a very costly operation in FPGA designs. High-frequency implementations of the classic digit-recurrence algorithms for division have long latencies (of the order of the number fraction bits) and consume large amounts of logic. Additionally, these implementations require important routing resources, making timing closure difficult in complete designs. In this paper we present two multiplier-based architectures for division which make efficient use of the DSP resources in recent Altera FPGAs. By balancing resource usage between logic, memory and DSP blocks, the presented architectures maintain high frequencies is full designs. Additionally, compared to classical algorithms, the proposed architectures have significantly lower latencies. The architectures target faithfully rounded results, similar to most elementary functions implementations for FPGAs but can also be transformed into correctly rounded architectures with a small overhead. The presented architectures are built using the Altera DSP Builder advanced framework and will be part of the default blockset.

关键词： Digital signal processing Polynomials Field programmable gate arrays Approximation error Memory management

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Low power implementation of a turbo-decoder on programmable architectures

Low power implementation of a turbo-decoder on programmable ...

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Asia and South Pacific Design Automation Conference

作者： F. Gilbert A. Worm N. Wehn Institute of Microelectronic Systems Department of Electrical Engineering and Information Technology University of Kaiserslautern Germany

ISBN: (纸本)0780366336

Low power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on the system level by the use of an intelligent cancellation technique, and on the implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of turbo-decoders based on voltage scheduling for third generation wireless systems.

关键词： Dynamic voltage scaling Turbo codes Iterative decoding Processor scheduling Forward error correction signal processing algorithms Channel coding Error correction Redundancy Bit error rate

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