We describe the VLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area. In particular, algorithms and VLSI architectures for s...
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ISBN:
(纸本)9783981080100
We describe the VLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area. In particular, algorithms and VLSI architectures for sphere decoding (SD) and K-best detection are considered, and the corresponding trade-offs between uncoded error-rate performance, silicon area, and throughput are explored. We show that SD with a per-block run-time constraint is best suited for practical implementations
The conventional resolution of individual emitters or frequencies within a cluster is limited by the physical dimensions and electrical aspects (such as the bandwidth) of a sensor system. Super-resolution describes al...
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The conventional resolution of individual emitters or frequencies within a cluster is limited by the physical dimensions and electrical aspects (such as the bandwidth) of a sensor system. Super-resolution describes algorithmic techniques that potentially enhance the conventional degree of resolution. Although there has been considerable research into super-resolution techniques (since 1970), there has, in contrast, been very little that addresses the fundamental bound of resolution performance that should theoretically be achievable by a 'perfect' algorithm in ideal conditions. The purpose of this paper is to present a generic method for predicting the fundamental resolution limit. We show that the resolution of closely-spaced signal waveforms is intrinsically linked to the signal-to-noise ratios of those signals. The method can be applied to individual spatial, temporal or spectral discriminants or to multi-discriminant systems. Loss of SNR resulting from the need to separate signals is derived both for the matched filter case and for eigen decomposition.
In this paper, we use the concept of evolutionary spectrum to solve key problems in array processing. We present Cross-power Evolutionary Periodogram for direction finding and blind separation of nonstationary signals...
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In this paper, we use the concept of evolutionary spectrum to solve key problems in array processing. We present Cross-power Evolutionary Periodogram for direction finding and blind separation of nonstationary signals. We model nonstationary signals received by each sensor in the array as a sum of complex sinusoids with time-varying amplitudes. These amplitudes carry information about the direction of arrival which may also be time-varying. We first estimate the time-varying amplitudes, then use the results for the estimation of evolutionary cross-power distributions of the sensor data. Next, using cross-power estimates at time-frequency samples of interest, we estimate the directions of arrival using one of the existing high resolution direction finding methods. If the directions are time-varying, we select time-frequency points around the time of interest. By carrying out the estimation at different times, we obtain the directions as a function of time. If the sources are stationary, then we can use all time-frequency points of interest for the estimation of fixed directions. We also use whitening and subspace methods to find the mixing matrix and separate the signals received by the array. Simulation examples illustrating the performances of the proposed algorithms are presented.
Artificial Intelligence has emerged as a transformative technology, revolutionizing numerous industries by enabling advanced automation, predictive analytics, and decision-making capabilities. For that Artificial Inte...
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ISBN:
(数字)9798331532833
ISBN:
(纸本)9798331532840
Artificial Intelligence has emerged as a transformative technology, revolutionizing numerous industries by enabling advanced automation, predictive analytics, and decision-making capabilities. For that Artificial Intelligence overruns many domains like telecommunication, smart manufacturing industry, autonomous machines, Automated Disease Diagnosis in Medical Imaging, defense, and others. On the other hand, the hardware implementation of Artificial Intelligence comes with certain challenges and constraints, especially in a critical area, which leverages machine learning algorithms and real-time data analysis to optimize production processes and improve overall efficiency. Statistical operations play a crucial role in various machine learning algorithms to understand, process data, or make predictions to optimize models. So, in this work, we developed a high-speed and low-area design and implemented statistical operations for image or signalprocessing using an FPGA Device. To enhance the performance, we develop different hardware architectures based on different levels of parallelism to process the statistical operations to compute the Mean, Variance, and RMS (Root Mean Square). These generic architectures work in parallel/pipeline architectures with and without memory. The proposed architectures implement an FPGA target (Intel/Altera Agilex 7: AGMH039R47A2E1V) using Altera Quartus prime pro edition version 23.4 and achieve an ultra-high throughput with low-area consumption compared to the state-of-art methods. For 480×640 image size, the mean calculation architecture involves 1498 logic registers, 1912 slice LUT, and just 29kbits memory and it operates at a maximum frequency of 406.5MHz. Additionally, for an 8×8 image size, we need 33 clock cycles to achieve the mean calculation and 33+1 clock cycles to complete the variance calculation, compared to other approaches that require more than 64 clock cycles.
We present the "direct inverse scale transform" which is the extension to the "direct scale transform" method originally proposed by Williams, Zalubas and Hero III (see advancedsignalprocessing A...
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We present the "direct inverse scale transform" which is the extension to the "direct scale transform" method originally proposed by Williams, Zalubas and Hero III (see advanced signal processing algorithms, architectures and implementations VI, SPIE, vol.2846, p.262-72, 1996). This scheme completes the calculation of analysis and synthesis equations for the scale transform pair which is suitable especially for non-integer values of dilation or compression of signals. Several examples of transformed and reconstructed synthetic and real 1-D and 2-D signals are included.
SPA (simple power analysis) attacks against RSA cryptosystems are enhanced by using chosen-message scenarios. One of the most powerful chosen-message SPA attacks was proposed by Yen et. al. in 2005, which can be appli...
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SPA (simple power analysis) attacks against RSA cryptosystems are enhanced by using chosen-message scenarios. One of the most powerful chosen-message SPA attacks was proposed by Yen et. al. in 2005, which can be applied to various algorithms and architectures, and can defeat the most popular SPA countermeasure using dummy multiplication. Special input values of -1 and a pair of -X and X can be used to identify squaring operations performed depending on key bit stream. However, no experimental result on actual implementation was reported. In this paper, we implemented some RSA processors on an FPGA platform and demonstrated that Yen's attack with a signal filtering technique clearly reveal the secret key information in the actual power waveforms.
System developers have found that exploiting parallel architectures for control systems is challenging and often the resulting implementations do not provide the expected performance advantages over traditional unipro...
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Previously, most mammalian auditory systems research has concentrated on human sensory perception whose frequencies are lower than 20 kHz. The implementations almost always used analog VLSI design. Due to the complexi...
Previously, most mammalian auditory systems research has concentrated on human sensory perception whose frequencies are lower than 20 kHz. The implementations almost always used analog VLSI design. Due to the complexity of the model, it is difficult to implement these algorithms using current digital technology. This paper introduces a simplified model of biosonic reception system in bats and its implementation in the ‘‘Chiroptera Inspired Robotic CEphaloid’’ (CIRCE) project. This model consists of bandpass filters, a half‐wave rectifier, low‐pass filters, automatic gain control, and spike generation with thresholds. Due to the real‐time requirements of the system, the system employs Butterworth filters and advanced field programmable gate array (FPGA) architectures to provide a viable solution. The ultrasonic signalprocessing is implemented on a Xilinx FPGA Virtex II device in real time. In the system, 12‐bit input echo signals from receivers are sampled at 1 M samples per second for a signal frequency range from 20 to 200 kHz. The system performs a 704‐channel per ear auditory pipeline operating in real time. The output of the system is a coded time series of threshold crossing points. Comparing hardware implementation with fixed‐point software, the system shows significant performance gains with no loss of accuracy.
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