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作者： Cai, Jingxiao University of Oklahoma

学位级别：博士

The objectives of this dissertation work are developing an enhanced intelligent radar signal and data processing framework for aviation hazard detection, classification and monitoring, and real-time implementation on massive parallel platforms. Variety of radar sensor platforms are used to prove the concept including airborne precipitation radar and different ground weather radars. As a focused example of the proposed approach, this research applies evolutionary machine learning technology to turbulence level classification for civil aviation. An artificial neural network (ANN) machine learning approach based on radar observation is developed for classifying the cubed root of the Eddy Dissipation Rate (EDR), a widely-accepted measure of turbulence intensity. The approach is validated using typhoon weather data collected by Hong Kong Observatory's (HKO) Terminal Doppler Weather Radar (TDWR) located near Hong Kong International Airport (HKIA) and comparing HKO-TDWR EDR$^{1/3}$ detections and predictions with in situ EDR$^{1/3}$ measured by commercial aircrafts. The testing results verified that machine learning approach performs reasonably well for both detecting and predicting tasks. As the preliminary step to explore the possibility of acceleration by integrating General Purpose Graphic processing Unit (GPGPU), this research introduces a practical approach to implement real-time processing algorithms for general surveillance radar based on NVIDIA graphical processing units (GPUs). The pulse compression algorithms are implemented using compute unified device architecture (CUDA) libraries such as CUDA basic linear algebra subroutines and CUDA fast Fourier transform library, which are adopted from open source libraries and optimized for the NVIDIA GPUs. For more advanced, adaptive processing algorithms such as adaptive pulse compression, customized kernel optimization is investigated. A statistical optimization approach is developed for this purpose without needing muc

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CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES: Security implementations for Hardware and Reprogrammable Devices

CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES: Se...

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作者： Tim Erhan Guneysu Ruhr University Bochum

学位级别：博士

With the rise of the Internet, the number of information processing systems has significantly increased in many fields of daily life. To enable commodity products to communicate, so- called embedded computing systems are integrated into these products. However, many of these small systems need to satisfy strict application requirements with respect to cost-efficiency and performance. In some cases, such a system also needs to drive cryptographic algorithms for maintaining data security – but without significantly impacting the overall system performance. With these constraints, most small microprocessors, which are typically employed in embedded systems, cannot provide the necessary number of cryptographic computations. Dedicated hard- ware is required to handle such computationally challenging cryptography. This thesis presents novel hardware implementations for use in cryptography and cryptanalysis. The first contribution of this work is the development of novel high-performance implementa- tions for symmetric and asymmetric cryptosystems on reconfigurable hardware. More precisely, most presented architectures target hardware devices known as Field Programmable Gate Ar- rays (FPGAs) which consist of a large number of generic logic elements that can be dynamically configured and interconnected to build arbitrary circuits. The novelty of this work is the us- age of dedicated arithmetic function cores – available in some modern FPGA devices – for cryptographic hardware implementations. These arithmetic functions cores (also denoted as DSP blocks) were originally designed to improve filtering functions in Digital signal processing (DSP) applications. The thesis at hand investigates how these embedded function cores can be used to significantly accelerate the operation of symmetric block ciphers such as AES (FIPS 197 standard) as well as asymmetric cryptography, e. g., Elliptic Curve Cryptography (ECC) over NIST primes (FIPS 186-2/3 standard). Graphics processing Units

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Computing methods for signal algebra operators: A DSP core implementations approach

Computing methods for signal algebra operators: A DSP core i...

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作者： Quinchanegua, Alberto University of Puerto Rico Mayaguez (Puerto Rico)

学位级别：M.S.

This document presents a methodology based on a signal algebra operator theoretic approach for the mathematical formulation of signal processing algorithms and efficient systematic procedures for mapping these algorithms to target hardware computing structures through iconic and functional programming techniques, and automatic core generation efforts. An algorithm development and implementation environment is described in this work as a central theme in studying DSP computing methods. This environment is an aggregate of the following items: a PC Workstation platform, MATLAB® tools, digital signal processing (DSP) microprocessor units, and field programmable gate array (FPGA) units. Special emphasis is given to the concepts of modularity and scalability during a hardware implementation. A main goal of this on going work is to establish formal links amongst the elements of the environment in order to assist in reducing the algorithm development and implementation time-line. The results presented here center on the formulation of a methodology for computing methods as an operator theoretic approach to the digital processing of signals, and on the study of the computing hardware structure and overall architecture of floating point DSP microprocessor units and FPGAs for the implementation of complex fast Fourier transform (FFT) cores. The new methodology presented in this work was successfully utilized for the generation of signal processing cores for DSP and FPGA hardware units in a signal algebra setting, with advantages such as improved latency time, and modular and reconfigurable features, which make the developed cores desirable for the implementation of more advanced digital signal processing applications.

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COARSE-GRAINED algorithms and implementations OF STRUCTURAL INDEXING-BASED OBJECT RECOGNITION ON INTEL TOUCHSTONE DELTA 12

COARSE-GRAINED ALGORITHMS AND IMPLEMENTATIONS OF STRUCTURAL ...

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Conference C on signal processing and Conference D on Parallel Computing, at the 12th IAPR International Conference on Pattern Recognition

作者： KHOKHAR, AA COOK, GW JAMIESON, LH DELP, EJ PURDUE UNIV DEPT ELECT ENGNW LAFAYETTEIN 47907

ISBN: (纸本)0818662751

In this paper, we present efficient parallel solutions for structural indexing-based object recognition on coarse-grained parallel machines. Based on the analysis using the C3-model, the parallel algorithm proposed in this paper takes O(Sk/p) computation units and O(p3,2) communication units on a p processor coarse-grained machine such that 1 ≤ p ≤ S, whereas the sequential solution takes O(Sk). The proposed solution is implemented on the Intel Touchstone Delta and performance results are shown. For a scene consisting of 160 feature points, the recognition phase takes 258 ms on a 64 processor Delta when the model database contains 256 models. The sequential algorithm takes approximately 4 seconds on a single node of the Delta. © 1994 IEEE.

关键词： Object recognition

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Accelerated AES implementations via generalized instruction set extensions

Accelerated AES implementations via generalized instruction ...

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作者： Elbirt, A.J. Department of Computer Science University of Massachusetts Lowell Lowell MA 01854 United States Department of Computer Science University of Massachusetts Lowell One University Avenue Lowell MA 01854 United States

Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers, including the advanced Encryption Standard (AES), have been proposed and implemented, using a wide and varied range of functional operations. Existing microprocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) processor cores presents the opportunity to augment existing datapaths with instruction set extensions to add acceleration modules in the form of new instructions. We will present a general purpose instruction set extension to a 32-bit SPARC V8 compatible processor core that accelerates the performance of Galois Field fixed field constant multiplication, a core element of the AES algorithm. This extension will be shown to accelerate AES encryption versus pure software implementations at a small hardware cost. This matches the improvement demonstrated in previously proposed AES-specific instruction set extensions while maintaining a generalized implementation format capable of supporting other algorithms that use Galois Field fixed field constant multiplication. © 2008 - IOS Press and the authors. All right reserved.

关键词： Cryptography

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Efficient Vectorized Architecture for Feedback Delay Network Reverberator with Policy Based Design 19

Efficient Vectorized Architecture for Feedback Delay Network...

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SPA 2015 signal processing algorithms, architectures, Arrangements, and Applications

作者： Gawlik, Ireneusz Pedzimaz, Tomasz Palka, Szymon Ziolko, Bartosz AGH Univ Sci & Technol Fac Comp Sci Elect & Telecommun Al Mickiewicza 30 PL-30059 Krakow Poland Techmo PL-30364 Krakow Poland

ISBN: (纸本)9781467375979

The Feedback Delay Network (FDN) is used as artificial digital reverberation algorithm. Being one of the most naturally sounding approaches it became widely implemented in many sound processing software products. Although FDN is a very potent tool in regards to artificial reverberation, achieving proper perceptual quality of acoustic simulation usually demands additional modifications to signal processing algorithms within delay lines, as well as on the input/output of FDN. This paper discusses efficient vectorized Architecture for FDN reverberator with policy based design to achieve modular implementation, allowing for compile time construction the FDN, without sacrificing top performance requirements.

关键词： Optimizations FDN policy-based design template metaprogramming SLIM C plus plus implementations

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Efficient Real-Time architectures and FPGA implementations of Histogram-Based Median Filters for High Definition Videos

Efficient Real-Time Architectures and FPGA Implementations o...

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作者： Goel, Anish Concordia University

学位级别：硕士

Digital filtering plays an important role in many signal processing applications. Filtering is performed to recover the original signal from its corrupted version. Median filter is a non-linear digital filter that replaces a sample in a given window by the median value of the samples in the window. For images corrupted with impulse noise, median filter provides a very high quality of filtered images. Several modifications of median filters have been proposed and implemented to achieve high image quality compared to that provided by conventional median filters. When these filters are implemented on hardware platforms such as FPGAs, the performance parameters, namely, the area, power and operating frequency should be taken into consideration in addition to the quality of the filtered image. Therefore, efficient implementation of median filters on FPGAs for image and video processing algorithms has been a topic of much interest. The existing hardware-based median filters for high definition video formats do not always satisfy the real-time throughput requirements or are inefficient with respect to hardware performance parameters, such as the area and frequency. This is due to the fact that most of the existing techniques use sorting-based median calculation, which results in a low hardware performance. In this thesis, architectures that use histogram-based median computation, which is a non-sorting-based operation, are designed with a view of efficient hardware implementation. This is carried out in two parts. We design and implement efficient architectures that satisfy the real-time throughput requirements of full high definition (FHD) videos in the first part and that of ultra high definition (UHD) videos in the second part. In the first part, an efficient real-time histogram-based median filter that uses the concept of bit-plane-slicing and adaptive switching median filter (ASMF) is designed and implemented on FPGAs. We term this architecture as hybrid architecture

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MICROWAVE DIVERSITY IMAGING AND AUTOMATED TARGET IDENTIFICATION BASED ON MODELS OF NEURAL NETWORKS

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PROCEEDINGS OF THE IEEE 1989年第5期77卷 670-681页

作者： FARHAT, NH Dept. of Electr. Eng. Pennsylvania Univ. Philadelphia PA

Radar targets can be identified by either forming images with sufficient resolution to be recognized by the human observer or by forming signatures or representations of the target for automated machine recognition. Tomographic microwave diversity imaging techniques that combine angular (aspect), spectral, and polarization degrees of freedom have been shown, as summarized in the first part of this paper, to be capable of producing images of the scattering centers of a target with near optical resolution. In the second part of the paper the author shows that collective nonlinear signal processing based on models of neural networks combined with the use of suitable target signatures (here sinogram representations) offer the promise of robust super-resolved target identification from partial information. Results presented are of numerical simulations for a neuromorphic processor where the neural net performs simultaneously the functions of data storage, processing, and recognition by automatically generating an identifying object label, and fast optoelectronic architectures and hardware implementations are briefly mentioned. Practical considerations and extensions to real systems are briefly discussed

关键词： 3D tomographic images RCS automated machine recognition automated target identification collective nonlinear signal processing computerised pattern recognition hardware implementations identifying object label microwave diversity imaging microwave imaging neural nets neural networks neuromorphic processor numerical simulations optoelectronic architectures partial information projection images radar cross-sections radar cross-sections radar targets sinogram representations target signatures telecommunications computing

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The Automated Compilation of Comprehensive Hardware Design Search Spaces of Algorithmic-Based implementations for FPGA Design Exploration

The Automated Compilation of Comprehensive Hardware Design S...

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作者： Michael A. Balog, III Drexel University

学位级别：博士

Over the past few years FPGA hardware has become a logical choice for imple- menting cutting-edge signal processing applications. While there have been advances in FPGA technology, the common process of creating specialized hardware imple- mentations for them is a manual one involving extensive design exploration. Design exploration is a process that requires a designer to look for designs that t a set of performance characteristics such as size, throughput, or power depending on the application and it can be the most time consuming step when creating FPGA hard- ware. This process is a nontrivial task that requires extensive background knowledge of both FPGA hardware and the application being implemented. While advances have been made in automating the process of design, there is still a gap between the application writers and hardware engineers that can be lled. This thesis presents a novel approach for automating the generation of hardware design search spaces that contain a comprehensive set of ways to implement signal processing algorithms with FPGAs. To accomplish this we generate a set of equiv- alent mathematical representations for an input equation via a novel declarative programming language that avoids a number of diculties associated with the im- perative languages used by previous approaches. We show that this equation space is bounded in terms of bracketing and ordering of mathematical operations, and that by changing the way an equation is written we can generate unique hardware instantiations (designs). The generated instantiations are mapped to heterogeneous computing architectures and written in a structural hardware descriptive language style to ensure that the intended instantiation will behave as predicted in hardware. A software system was created based on this approach that generates an equation space for varying numbers of summed multiplications and converts each representa- tion into a comprehensive hardware design search space that can be a

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Matrix approach for fast implementations of logarithmic MAP decoding of turbo codes

Matrix approach for fast implementations of logarithmic MAP ...

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IEEE Pacific Rim Conference on Communications, Computers and signal processing

作者： Duanyi Wang H. Kobayashi Department of Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)0780370805

This paper describes two new matrix transform algorithms for the max-log-MAP decoding of turbo codes. In the proposed algorithms, the successive decoding procedures carried out in the conventional max-log-MAP algorithm are performed in parallel, and well formulated into a set of simple and regular matrix operations, which can therefore considerably speed up the decoding operations and reduce the computational complexity. The matrix max-log-MAP algorithms also maintain the advantage of the general logarithmic MAP like algorithms in avoiding complex numerical representation problems. They particularly facilitate the implementations of the logarithmic MAP like algorithms in special-purpose parallel processing VLSI hardware architectures. The matrix algorithms also allow simple implementations by using shift registers. The proposed implementation architectures for the matrix max-log-MAP decoding can effectively reduce the memory capacity and simplify the data accesses and transfers required by the conventional max-log-MAP as well as MAP algorithms.

关键词： Turbo codes Very large scale integration Iterative algorithms Computational complexity Parallel processing Hardware Iterative decoding Computer architecture Shift registers Circuits

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