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International Symposium on signals, Circuits and Systems (ISSCS)

作者： Jose M. F. Moura Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

I introduce SPIRAL (***), a generator of libraries of linear signal processing algorithms like linear transforms, including the discrete Fourier transform, the discrete cosine transform, filters, or wavelets, as well as applications lke JPEG2000, Viterbi decoding, and SAR image formation algorithms. SPIRAL is a new breed of intelligent compilers that couples domain knowledge, computer architecture modeling, machine learning methodologies, and compiler technology to generate automatically highly tuned SW codes and very efficient HW IP cores. SPIRAL produces automatically C code with embedded vector and parallel instructions for multicore or multiprocessor architectures, or netlists for FPGA implementations. SPIRAL can optimize for or trade among a range of criteria including runtime, power/energy, accuracy, or area. SPIRAL has been benchmarked against expert hand tuned implementations and has been licensed as a tool by INTEL.

关键词： signal processing algorithms Algebra signal generators Spirals Discrete Fourier transforms Discrete wavelet transforms Computer architecture Libraries Fourier transforms Discrete cosine transforms

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Review of Hardware implementations of Convolution for Discrete Wavelet Transform

Review of Hardware Implementations of Convolution for Discre...

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North Karnataka Subsection Flagship International Conference (NKCon), IEEE

作者： Ramprakash C Skanda Prasad Pratyusha R Raghu Jayaramu Department of Electronics and Communication Engineering The National Institute of Engineering Mysuru India

Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. This work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform (DWT). For such applications, read-only memory (ROM)-based architectures are known for their speed and performance. Two such architectures-distributed arithmetic (DA) and residue number system (RNS) are reviewed. Hardware utilization of both architectures using similar inputs and parameters on the Digilent Nexys-A7-100T field programmable gate array (FPGA) platform using Xilinx Vivado and other open-source tools are reported. Distributed arithmetic (DA) is found to be favourable for small input lengths, but residue number system (RNS) will surpass it for larger input lengths. A parallel distributed arithmetic (DA) implementation is also implemented, that offers significant computational speed-up at minimal power cost.

关键词： Convolution signal processing algorithms Computer architecture Transforms Digital signal processing Logic gates Discrete wavelet transforms

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Parallel implementations with low-complexity of rotation-based adaptive filters

Parallel implementations with low-complexity of rotation-bas...

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IEEE Workshop on signal processing Systems (SIPS)

作者： M. Bhouri Institute Supérieur d'Informatique et de Mathématiques

This paper propose a new parallel implementation of some rotation-based adaptive filters (Bhouri, M, 2000). These filters are characterized by a robust behavior to input signal correlation (Bhouri, M, et al, 1998) and good numerical properties. However, their implementations have reduced complexities. The circuits based on these block-diagonal adaptive algorithms use less computing cells than the systolic circuit of the QR-RLS algorithm. Nevertheless, these new and low-complexity architectures have no longer a pipeline structure.

关键词： Adaptive filters Resonance light scattering Robustness Circuits Least squares approximation Filtering algorithms Adaptive algorithm Systolic arrays Computer architecture Pipelines

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FPGA based hardware architectures for iterative algorithms implementations

FPGA based hardware architectures for iterative algorithms i...

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International Conference on Telecommunications and signal processing (TSP)

作者： Bogdan Belean Monica Borda Adrian Bot Department of Mass Spectrometry National Institute for Research and Development of Isotopic and Molecular Technologies Cluj-Napoca Romania Department of Communication Technical University of Cluj-Napoca Cluj-Napoca Romania

The paper describes the FPGA technology together with its possibility to exploit spatial and temporal parallelism in order to implement hardware architectures for iterative algorithms. The development of hardware architecture using FPGA technology represents a reliable solution in case of various applications where fast processing in case of iterative algorithms it's mandatory. Two applications are presented where the FPGA technology is used for processing. Thus, on one hand, automatic microarray grid alignment is performed using FPGA based hardware architecture, while on the other hand, an FPGA based LDPC decoder implementation is proposed in order to improve the decoder throughput compared to state of the art approaches.

关键词： Parity check codes Field programmable gate arrays Decoding Hardware Image processing Electric shock Computer architecture

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Modified Distributed Arithmetic Concept for implementations Targeted at Heterogeneous FPGAs

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INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS 2010年第4期56卷 345-350页

作者： Rawski, Mariusz Warsaw Univ Technol Inst Telecommun Nowowiejska 15-19 PL-00665 Warsaw Poland

Distributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.

关键词： Distributed arithmetic FPGA heterogeneous programmable structures

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Configurable computing and sonar processing - architectures and implementations

Configurable computing and sonar processing - architectures ...

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Asilomar Conference on signals, Systems & Computers

作者： B.E. Nelson Department of Electrical and Computer Engineering Brigham Young University Provo UT USA

ISBN: (纸本)078037147X

Sonar beamforming is an ideal application for reconfigurable computing due to its high available levels of parallelism, relatively low sample rates and modest word sizes. We describe a family of beamforming algorithms and their implementation using configurable computing technology. These include algorithms for time-delay, frequency-domain and matched field beamforming. Configurable computing architectures appropriate for each are described and the tradeoffs associated with the mapping of each to concrete platforms is discussed.

关键词： Sonar Computer architecture Field programmable gate arrays Parallel processing Digital signal processing Array signal processing Logic arrays Wires Distributed computing Military computing

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Learning Efficient Sparse and Low Rank Models

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IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE 2015年第9期37卷 1821-1833页

作者： Sprechmann, P. Bronstein, A. M. Sapiro, G. Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA Tel Aviv Univ Sch Elect Engn IL-69978 Tel Aviv Israel

Parsimony, including sparsity and low rank, has been shown to successfully model data in numerous machine learning and signal processing tasks. Traditionally, such modeling approaches rely on an iterative algorithm that minimizes an objective function with parsimony-promoting terms. The inherently sequential structure and data-dependent complexity and latency of iterative optimization constitute a major limitation in many applications requiring real-time performance or involving large-scale data. Another limitation encountered by these modeling techniques is the difficulty of their inclusion in discriminative learning scenarios. In this work, we propose to move the emphasis from the model to the pursuit algorithm, and develop a process-centric view of parsimonious modeling, in which a learned deterministic fixed-complexity pursuit process is used in lieu of iterative optimization. We show a principled way to construct learnable pursuit process architectures for structured sparse and robust low rank models, derived from the iteration of proximal descent algorithms. These architectures learn to approximate the exact parsimonious representation at a fraction of the complexity of the standard optimization methods. We also show that appropriate training regimes allow to naturally extend parsimonious models to discriminative settings. State-of-the-art results are demonstrated on several challenging problems in image and audio processing with several orders of magnitude speed-up compared to the exact optimization algorithms.

关键词： Parsimonious modeling sparse and low-rank models NMF deep learning real-time implementations big data proximal methods

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RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC dec...

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Conference on Design and architectures for signal and Image processing

作者： Endri Bezati Marco Mattavelli Mickaël Raulet Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland IETR/INSA Rennes France

This paper describes the implementation of the MPEG AVC CABAC entropy decoder using the RVC-CAL dataflow programming language. CABAC is the Context based Adaptive Binary Arithmetic Coding entropy decoder that is used by the MPEG AVC/H.264 main and high profile video standard. CABAC algorithm provides increased compression efficiency, however presents a higher complexity compared to other entropy coding algorithms. This implementation of the CABAC entropy decoder using RVC-CAL proofs that complex algorithms can be implemented using a high level design language. This paper analyzes in detail two possible methods of implementing the CABAC entropy decoder in the dataflow paradigm.

关键词： Decoding Automatic voltage control Entropy Encoding Transform coding Context Syntactics

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Graph Theoretical Representation of Grid-based ANN architectures for VLSI implementations

Graph Theoretical Representation of Grid-based ANN Architect...

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Congress on Evolutionary Computation

作者： S.C. Stilkerich EADS-Corporate Research Center Munich Germany

The System-on-Chip design of purely digital architectures, which are based on massively parallel Markov random field (MRF) processing principles is so far an unstructured, time consuming, fault-prone and complex task. Up to now a toolkit is not available to systematically support the VLSI design task in a single coherent environment and along a seamless design flow for various digital semiconductor-technologies. In this contribution we report on a completely technology-independent and graph-theoretical approach for the VLSI design of massively parallel MRF processing devices. The paper is finalized by selected results, which show generated graphs, synthesis results and prototypical implementations in FPGA technologies. All together these results demonstrate the ability of the proposed graph-theoretical approach and manifest the industrial relevance of the developed tool-kit.

关键词： Very large scale integration Image analysis Markov random fields signal processing algorithms signal processing Space technology Radiation hardening Field programmable gate arrays Entropy Parallel processing

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Performance and Power Analysis of Parallelized implementations on an MPCore Multiprocessor Platform

Performance and Power Analysis of Parallelized Implementatio...

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International Conference on Embedded Computer Systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： H. Blume J. v. Livonius L. Rotenberg T. G. Noll H. Bothe J. Brakensiek Chair for Electrical Engineering and Computer Systems RWTH Aachen University Aachen Germany Nokia Research Center Bochum Germany

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM 11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For paralllelization issues the OpenMP programming model has been used which can be efficiently applied on C- level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.

关键词： Performance analysis Digital signal processing Software algorithms signal processing algorithms Multicore processing signal analysis Algorithm design and analysis Software prototyping Prototypes Yarn

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