检索结果-内蒙古大学图书馆

International Conference on advanced Technologies for signal and Image processing (ATSIP)

作者： Nejmeddine Alimi Younes Lahbib Mohsen Machhout Rached Tourki Faculty of Sciences of Tunis University of Tunis EI Manar Tunis Tunisia Electronics and Micro-Electronics Laboratory University of Monastir Monastir Tunisia National Engineering School of Carthage University of Carthage Tunis Tunisia

ISBN: (纸本)9781467385275

Elliptic Curve Cryptography have known, in recent years, an increasing success in security applications thanks to their advantages such as a short keys size with a high security level. Their popularity has led to various implementations in terms of algorithms, curves, coordinate systems, platforms, etc. The aim of this work is first to explore actual trends of ECC-based implementations in different platforms through a review of a number of works. Secondly, to identify and gather the criteria and corresponding metrics used to evaluate the performance of these implementations. We also propose a platform for design exploration and evaluation of ECC designs.

关键词： Elliptic curve cryptography Program processors Hardware Field programmable gate arrays Elliptic curves

来源：评论

学校读者我要写书评

暂无评论

Performance and Power Analysis of Parallelized implementations on an MPCore Multiprocessor Platform

Performance and Power Analysis of Parallelized Implementatio...

引用

International Conference on Embedded Computer Systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： H. Blume J. v. Livonius L. Rotenberg T. G. Noll H. Bothe J. Brakensiek Chair for Electrical Engineering and Computer Systems RWTH Aachen University Aachen Germany Nokia Research Center Bochum Germany

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM 11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For paralllelization issues the OpenMP programming model has been used which can be efficiently applied on C- level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.

关键词： Performance analysis Digital signal processing Software algorithms signal processing algorithms Multicore processing signal analysis Algorithm design and analysis Software prototyping Prototypes Yarn

来源：评论

学校读者我要写书评

暂无评论

Automatic generation of implementations for DSP transforms on fused multiply-add architectures

Automatic generation of implementations for DSP transforms o...

引用

International Conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Y. Voronenko M. Puschel Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Many modern computer architectures feature fused multiply-add (FMA) instructions, which offer potentially faster performance for numerical applications. For DSP transforms, compilers can only generate FMA code to a very limited extent because optimal use of FMAs requires modifying the chosen algorithm. In this paper, we present a framework for automatically generating FMA code for every linear DSP transform, which we implemented as an extension to the SPIRAL code generation system. We show that for many transforms and transform sizes, our generated FMA code matches the best-known hand-derived FMA algorithms in terms of arithmetic cost. Further, we present actual runtime results that show the speed-up obtained by using FMA instructions.

关键词： Digital signal processing signal processing algorithms Discrete cosine transforms Spirals Costs Discrete Fourier transforms Computer architecture Arithmetic Discrete transforms Runtime

来源：评论

学校读者我要写书评

暂无评论

Tightly-coupled parallel implementations of an avionics algorithm

Tightly-coupled parallel implementations of an avionics algo...

引用

IEEE National Conference on Aerospace and Electronics (NAECON)

作者： J. Carter S. Hary Avionics Directorate Information Processing Branch Wright Laboratories OH USA

It has long been recognized that there exists an upper bound on the computing speed attainable with uniprocessor architectures. The state of the industry has been such that the regular performance improvements in silicon technology have kept the need for widespread use of tightly-coupled parallel architectures to a minimum. However, with the increasing computational demands placed upon uniprocessor architectures, the time is rapidly approaching when tightly-coupled parallel architectures will be required. In order to demonstrate the effectiveness of using tightly-coupled parallel architectures for avionics applications, a representative avionics algorithm was parallelized and implemented on three parallel topologies constructed from Texas Instruments' parallel digital signal processor TMS320C40. The algorithm's execution time was measured and estimated on different parallel topologies, including ring, four nearest neighbor mesh, and eight nearest neighbor mesh. It was found that due to the low communication-to-computation ratio of the algorithm, near-linear speedups were obtained for the parallel implementations of the algorithm.< >

关键词： Aerospace electronics signal processing algorithms Parallel architectures Computer architecture Topology Nearest neighbor searches Upper bound Silicon Concurrent computing Instruments

来源：评论

学校读者我要写书评

暂无评论

HIGH THROUGHPUT FILTER ARCHITECTURE FOR OPTIMAL FPGA-BASED implementations

引用

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2013年第5期22卷 1350034-1350034页

作者： Kamboh, Hamid M. Khan, Shoab A. Ctr Adv Studies Engn Dept Elect & Comp Engn Islamabad 44000 Pakistan Ctr Adv Res Engn Islamabad 44000 Pakistan

Modern field programmable gate arrays (FPGAs) offer built in support for efficient implementation of signal processing algorithms in the form of specialized embedded blocks such as high speed carry chains, specialized shift registers, adders, multiply accumulators (MAC) and block memories. These dedicated elements provide increased computational power and are used for efficient implementation of computationally extensive algorithms. This paper proposes a novel algorithm and architecture for the design and implementation of high performance intermediate frequency (IF) filters on FPGAs. In this research, we have proposed innovative design methodologies for generation of optimal feed forward and recursive architectures to be mapped on a family of FPGAs. Keeping in perspective the limited number of registers within the embedded blocks, the new methodology applies transformations to achieve higher throughput by applying various optimizations to the design algorithm. Implementation options include systolic MAC, transpose direct form MAC, canonic signed digit and distributed arithmetic based filters to suite the most economical FPGA implementation. The paper demonstrates the methodology and shows its applicability by synthesizing the designs and comparing the results to a number of traditional architectures and intellectual property cores. Using Xilinx Virtex-5 FPGA, our results show a throughput improvement between 7% and 30% with an average improvement of 16% over traditional implementations of these designs.

关键词： FPGA mapping retiming unfolding look ahead transform FIR & IIR filter distributed arithmetic

来源：评论

学校读者我要写书评

暂无评论

SIMPLIFIED FLOATING-POINT DIVISION AND SQUARE ROOT

SIMPLIFIED FLOATING-POINT DIVISION AND SQUARE ROOT

引用

IEEE International Conference on Acoustics, Speech, and signal processing (ICASSP)

作者： Viitanen, Timo Jaaskelainen, Pekka Esko, Otto Takala, Jarmo Tampere Univ Technol Dept Comp Syst FIN-33101 Tampere Finland

ISBN: (纸本)9781479903566

Digital signal processing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent research shows that floating-point arithmetic can be made competitive by using a reduced-precision format instead of, e. g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difficulties associated with fixed-point arithmetic. This paper investigates the effects of simplified floating-point arithmetic applied to an FMA-based floating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overflow-related errors with inexpensive exponent-manipulation special instructions.

关键词： Floating-point arithmetic accelerator architectures fused multiply-add digital signal processing implementations low-power design

来源：评论

学校读者我要写书评

暂无评论

Compressive Sensing for Streaming signals using the Streaming Greedy Pursuit

Compressive Sensing for Streaming Signals using the Streamin...

引用

MILCOM Military Communications Conference

作者： Boufounos, Petros T. Asif, M. Salman Mitsubishi Elect Res Labs Cambridge MA 02139 USA Georgia Inst Technol Sch ECE Atlanta GA 30332 USA

ISBN: (纸本)9781424481804

Compressive Sensing (CS) has recently emerged as significant signal processing framework to acquire and reconstruct sparse signals at rates significantly below the Nyquist rate. However, most of the CS development to-date has focused on finite-length signals and representations. In this paper we present a new CS framework and a greedy reconstruction algorithm, the Streaming Greedy Pursuit (SGP), explicitly designed for streaming applications and signals of unknown length. Our sampling framework is designed to be causal and implementable using existing hardware architectures. Furthermore, our reconstruction algorithm provides explicit computational guarantees, which makes it appropriate for real-time system implementations. Our experimental results on very long signals demonstrate the good performance of the SGP and validate our approach.

关键词： CS framework Nyquist rate SGP compressive sensing computational guarantees finite-length signals greedy algorithms greedy reconstruction algorithm hardware architectures real-time system implementations signal acquisition signal detection signal processin

来源：评论

学校读者我要写书评

暂无评论

Hardware implementations of computer-generated holography: a review

引用

OPTICAL ENGINEERING 2020年第10期59卷 102413-102413页

作者： Wang, Youchao Dong, Daoming Christopher, Peter J. Kadis, Andrew Mouthaan, Ralf Yang, Fan Wilkinson, Timothy D. Univ Cambridge Ctr Mol Mat Photon & Elect Dept Engn Cambridge England

Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations. (C) 2020 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： computer-generated holography central processing unit graphics processing unit field-programmable gate array digital signal processor hardware accelerator holography system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Fast MPEG-4 motion estimation: Processor based and flexible VLSI implementations

引用

JOURNAL OF VLSI signal processing SYSTEMS FOR signal IMAGE AND VIDEO TECHNOLOGY 1999年第1期23卷 67-92页

作者： Kuhn, PM Sony Corp Corp R&D Labs Tokyo Japan Tech Univ Munich D-8000 Munich Germany

MPEG-4 is a new multimedia standard combining interactivity, object-based natural and synthetic digital video, audio and computer-graphics. For the implementation of the video part of the MPEG-4 standard a high degree of flexibility is required, where the motion estimation requires the highest part of the computational power. Therefore, in this paper fast algorithms for MPEG-4 motion estimation are evaluated in terms of visual quality and computational power requirements for processor based implementations. Due to the object-based nature of MPEG-4 also new VLSI architectures for MPEG-4 motion estimation are required. Therefore known motion estimation architectures are evaluated on their capability of being modified for MPEG-4 support. Based on this evaluation a new dedicated, but flexible MPEG-4 motion estimation architecture targeted for low-power handheld applications is presented, which resulted to be advantageous to processor based implementations by magnitudes of order.

关键词： MPEG-4 motion estimation VLSI processor algorithm complexity analysis

来源：评论

学校读者我要写书评

暂无评论

Systolic implementations of up/down-dating Cholesky factorization using vectorized Gram-Schmidt pseudo orthogonalization

引用

Journal of VLSI signal processing Systems for signal, Image, and Video Technology 1991年第3期3卷 151-161页

作者： Hsieh, S.F. Liu, K.J.R. Yao, K. Natl Chiao Tung Univ Hsinchu Taiwan

We propose a new class of hyperbolic Gram-Schmidt methods to simultaneously update and downdate the Cholesky factor of a sample covariance matrix efficiently with applications to sliding window recursive least squares (RLS) filtering problems. Several vectorized versions of this Gram-Schmidt approach are introduced, which include conventional column-updating, modified row/column-updating, and square-root-free methods. Comparisons to the existing known methods, such as Householder transformation and Givens rotation, are also given. Upon further reformulating these algorithms, a systolic triarray structure is proposed to facilitate VLSI implementations.

关键词： Mathematical Techniques

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：