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European signal processing Conference (EUSIPCO)

作者： Daniele Bagni Antonio Borneo Luca Celetto Advanced System Technology STMicroelectronics Agrate Brianza MI Italy

In this paper we describe two efficient software implementations of bi-dimensional IDCT (Inverse Discrete Cosine Transform). Instead of using a traditional separation into eight horizontal and vertical mono-dimensional IDCT stages, we apply a novel approach to directly represent the bi-dimensional IDCT into only eight mono-dimensional units followed by a network of addition and subtraction operations. We have then optimized this method in pure ANSI-C for 32-bit architecture VLIW (Very Long Instruction Word) processors. By arranging the network structure in a proper way to exploit sub-word parallelism and by defining totally new multimedia instructions, we have implemented a second version that is 23% more efficient than the previous one. Our fixed-point arithmetic IDCT implementations are fully compliant with the IEEE 1180 standard, as required by most of the video compression standards.

关键词： Discrete cosine transforms VLIW Program processors Algorithm design and analysis signal processing algorithms Standards

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Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

Improved parameterized efficient FPGA implementations of par...

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IEEE International Symposium on signal processing and Information Technology (ISSPIT)

作者： Sami Hasan Said Boussakta Alex Yakovlev School of Electrical Electronic and Computer Engineering University of Newcastle UK

Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. This improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6xc6vlX130Tl-1lff1156 FPGA board to achieve lower power consumption of (820 mW) and a (27%-44%) less device utilization at a maximum frequency of up to (231 MHz) using Xilinx System Generator. The improved parameterized FPGA implementation is a system-level abstraction of hardware-oriented parallel programming, as an alternative to gate-level Hardware Descriptive Language (HDL), to satisfy the high performance computation of parallel multidimensional filtering algorithms at a minimal development-to-market time.

关键词： Delay Finite impulse response filter

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Coding algorithms and VLSI implementations for digital TV and HDTV satellite broadcasting

European transactions on telecommunications and related tech...

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European transactions on telecommunications and related technologies 1993年第1期4卷 11-21页

作者： Musmann, Hans Georg Pirsch, Peter Univ of Hannover Hannover Germany

Source coding techniques for reducing the bit rates of TV and HDTV signals are presented and discussed with respect to satellite broadcasting applications. The source coding techniques require transmission bit rates of 9 Mbit/s for a TV and 45 Mbit/s for an HDTV signal in order to provide distribution quality as required for broadcasting. Also three scalable coding schemes are outlined which allow graceful degradations at the boundary of the broadcasting service area by a transition from a HDTV to TV picture resolution. VLSI implementations of TV and HDTV decoders have been investigated in order to achieve compact and low cost realization. It is shown that the silicon area of VLSI devices can be kept small by choosing algorithms with small signal processing requirements and by taking advantage of a priori known features. VLSI architectures for the implementation of subband filters and DCT are discussed as key components.

关键词： Satellite communication systems

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Generic High-Speed Design with Low-Area implementations of Statistical Operations Based on an FPGA Device

Generic High-Speed Design with Low-Area Implementations of S...

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International Symposium on Symbolic and Numeric algorithms for Scientific Computing (SYNASC)

作者： Mouhamad Chehaitly Jorge Querol Praveen Vummadisetty Symeon Chatzinotas SnT University of Luxembourg Luxembourg

ISBN: (数字)9798331532833

ISBN: (纸本)9798331532840

Artificial Intelligence has emerged as a transformative technology, revolutionizing numerous industries by enabling advanced automation, predictive analytics, and decision-making capabilities. For that Artificial Intelligence overruns many domains like telecommunication, smart manufacturing industry, autonomous machines, Automated Disease Diagnosis in Medical Imaging, defense, and others. On the other hand, the hardware implementation of Artificial Intelligence comes with certain challenges and constraints, especially in a critical area, which leverages machine learning algorithms and real-time data analysis to optimize production processes and improve overall efficiency. Statistical operations play a crucial role in various machine learning algorithms to understand, process data, or make predictions to optimize models. So, in this work, we developed a high-speed and low-area design and implemented statistical operations for image or signal processing using an FPGA Device. To enhance the performance, we develop different hardware architectures based on different levels of parallelism to process the statistical operations to compute the Mean, Variance, and RMS (Root Mean Square). These generic architectures work in parallel/pipeline architectures with and without memory. The proposed architectures implement an FPGA target (Intel/Altera Agilex 7: AGMH039R47A2E1V) using Altera Quartus prime pro edition version 23.4 and achieve an ultra-high throughput with low-area consumption compared to the state-of-art methods. For 480×640 image size, the mean calculation architecture involves 1498 logic registers, 1912 slice LUT, and just 29kbits memory and it operates at a maximum frequency of 406.5MHz. Additionally, for an 8×8 image size, we need 33 clock cycles to achieve the mean calculation and 33+1 clock cycles to complete the variance calculation, compared to other approaches that require more than 64 clock cycles.

关键词： Industries Machine learning algorithms Computer architecture Throughput Hardware Real-time systems Artificial intelligence Root mean square Field programmable gate arrays Clocks

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Accelerated AES implementations via generalized instruction set extensions

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JOURNAL OF COMPUTER SECURITY 2008年第3期16卷 265-288页

作者： Elbirt, A. Univ Massachusetts Dept Comp Sci One Univ Ave Lowell MA 01854 USA

Efficient implementation of block ciphers is critical towards achieving both high security and highspeed processing. Numerous block ciphers, including the advanced Encryption Standard (AES), have been proposed and implemented, using a wide and varied range of functional operations. Existing microprocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) processor cores presents the opportunity to augment existing datapaths with instruction set extensions to add acceleration modules in the form of new instructions. We will present a general purpose instruction set extension to a 32-bit SPARC V8 compatible processor core that accelerates the performance of Galois Field fixed field constant multiplication, a core element of the AES algorithm. This extension will be shown to accelerate AES encryption versus pure software implementations at a small hardware cost. This matches the improvement demonstrated in previously proposed AES-specific instruction set extensions while maintaining a generalized implementation format capable of supporting other algorithms that use Galois Field fixed field constant multiplication.

关键词： Cryptography AES block cipher Galois Field

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Generating High-Performance Number Theoretic Transform implementations for Vector architectures

Generating High-Performance Number Theoretic Transform Imple...

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IEEE Conference on High Performance Extreme Computing (HPEC)

作者： Naifeng Zhang Austin Ebel Negar Neda Patrick Brinich Benedict Reynwar Andrew G. Schmidt Mike Franusich Jeremy Johnson Brandon Reagen Franz Franchetti Carnegie Mellon University New York University Drexel University USC Information Sciences Institute SpiralGen Inc.

Fully homomorphic encryption (FHE) offers the ability to perform computations directly on encrypted data by encoding numerical vectors onto mathematical structures. However, the adoption of FHE is hindered by substantial overheads that make it impractical for many applications. Number theoretic transforms (NTTs) are a key optimization technique for FHE by accelerating vector convolutions. Towards practical usage of FHE, we propose to use SPIRAL, a code generator renowned for generating efficient linear transform implementations, to generate high-performance NTT on vector architectures. We identify suitable NTT algorithms and translate the dataflow graphs of those algorithms into SPIRAL's internal mathematical representations. We then implement the entire workflow required for generating efficient vectorized NTT code. In this work, we target the Ring processing Unit (RPU), a multitile long vector accelerator designed for FHE computations. On average, the SPIRAL-generated NTT kernel achieves a 1.7x speedup over naive implementations on RPU, showcasing the effectiveness of our approach towards maximizing performance for NTT computations on vector architectures.

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Enhanced power analysis attack using chosen message against RSA hardware implementations

Enhanced power analysis attack using chosen message against ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Atsushi Miyamoto Naofumi Homma Takafumi Aoki Akashi Satoh Graduate School of Information Sciences University of Tohoku Sendai Japan National Institute for Advanced Industrial Science and Technology Tokyo Japan

SPA (simple power analysis) attacks against RSA cryptosystems are enhanced by using chosen-message scenarios. One of the most powerful chosen-message SPA attacks was proposed by Yen et. al. in 2005, which can be applied to various algorithms and architectures, and can defeat the most popular SPA countermeasure using dummy multiplication. Special input values of -1 and a pair of -X and X can be used to identify squaring operations performed depending on key bit stream. However, no experimental result on actual implementation was reported. In this paper, we implemented some RSA processors on an FPGA platform and demonstrated that Yen's attack with a signal filtering technique clearly reveal the secret key information in the actual power waveforms.

关键词： Hardware Public key cryptography Information analysis Field programmable gate arrays Power measurement Electronic mail signal processing Information filtering Information filters Power dissipation

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signal processor architectures and implementations based upon gallium arsenide digital integrated circuits: The need for a wholistic design approach

Signal processor architectures and implementations based upo...

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International Electron Devices Meeting (IEDM)

作者： B.K. Gilbert Special Purpose Processor Development Group Mayo Foundation Rochester MN USA

The emerging Gallium Arsenide digital integrated circuit technology is rapidly becoming well enough established that designers of signal and data processors are planning its incorporation into advanced computational engines of all types. An examination of the characteristics of preset and future generation GaAs integrated circuits indicates that they will emphasize moderate on-chip gate counts and high gate speeds. Complete advantage can be taken of GaAs digital technology only if traditional signal processor architectures are completely recast at the memory layout, logic design, arithmetic implementation, and system architecture levels, and if these issues are considered in combination with system, logic boars, and chip layout and packaging constraints in a single integrated approach.

关键词： signal processing Gallium arsenide Digital integrated circuits signal design Computer architecture Integrated circuit technology Logic design Process planning Technology planning Engines

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Interactive optimization and massively parallel implementations of video compression algorithms

Interactive optimization and massively parallel implementati...

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IEEE International Conference on Image processing

作者： H. Nicolas F. Jordan CRAY Research EPF Lausanne Lausanne Switzerland Signal Processing Laboratory EPF Lausanne Lausanne Switzerland

This paper presents a new technique which allows interactive optimization of video compression algorithms using massively parallel computers such as the CRAY T3D. This work aims to exploit as much as possible the parallel nature of digital image processing algorithms to obtain almost real-time computing with the flexibility of a software implementation. Thanks to this low computation time, interactive tools have been developed which allow easy and fast visual evaluation of image quality. This leads to significant productivity gain when developing new video compression techniques. Our approach has been validated on advanced region-based video compression algorithms. The interactive facilities offered by the proposed technique permit the accurate optimization of the algorithm parameters in few minutes, where several days were previously needed. Depending on the complexity of the compression algorithms, 8-12 images are compressed, decompressed and visualized per second.

关键词： Video compression signal processing algorithms Compression algorithms Image coding Concurrent computing Visualization PSNR Image sequences Workstations Digital images

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Efficient implementations of mobile video computations on domain-specific reconfigurable arrays 04

Efficient implementations of mobile video computations on do...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Sami Khawam Sajid Baloch Arjun Pai Imran Ahmed Nizamettin Aydin Tughrul Arslan Fred Westall School of Electronics and Engineering University of Edinburgh Edinburgh UK Institute for System Level Integration Alba Center Livingston UK EPSON Scotland Design Centre Livingston UK

ISBN: (纸本)9780769520858

Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific reconfigurable arrays that have demonstrated up to 75% reduction in power consumption when compared to generic FPGA architecture, which makes them suitable for portable devices. This paper presents and compares different configurations of the arrays to efficiently implementing DCT and motion estimation algorithms. A number of algorithms are mapped into the various reconfigurable fabrics demonstrating the flexibility of the new reconfigurable SoC architecture and its ability to support a number of implementations having different performance characteristics.

关键词： Mobile computing Discrete cosine transforms signal processing algorithms Energy consumption Field programmable gate arrays Computer architecture Motion estimation Portable computers MPEG 4 Standard Hardware

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