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International Conference on Control 1991. Control '91

作者： D. Lawrie P. Fleming University of Wales UK

ISBN: (纸本)0852965095

To implement the Kalman filter, a number of matrix and vector manipulations must be executed within each sample period. Consequently, a drawback of the algorithm is that it is computationally intensive, requiring O(n/sup 3/) operations for each estimate of the n element state vector. Thus, parallel versions of the Kalman filter have been developed in order to reduce execution times and enable the algorithm to be implemented in an increased range of real-time applications. The paper investigates the potential of a 'fine-grain', parallel processing architecture, i.e. the GAPP chip (geometric arithmetic parallel processor), for implementing the Kalman filter algorithm.< >

关键词： Complexity theory Digital signal processors Kalman filtering Parallel architectures Parallel processing

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Characterization of Baseband implementations Using Energy Efficiency Metric Based Quantification

Characterization of Baseband Implementations Using Energy Ef...

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International Conference on Devices and Communications (ICDeCom)

作者： Hari Krishna Boyapati R. V. Raja Kumar Saswat Chakrabarti G S S School of Telecommunications Indian Institute of Technology Kharagpur India Indian Institute of Technology Delhi New Delhi Delhi IN

Energy consumption is an issue in general in information and communication technologies (ICT), but also cellular communications in particular. Base station sites are the main energy consumers in a mobile network. Their energy consumption significantly contributes to green house gas (Co 2 ) emissions. It has been found that digital baseband is the main contributor to dynamic part of the power consumption in new base station deployments due to its explosive computational complexity. Hence, the implementations of baseband subsystem need to be energy efficient in advanced systems and thus to reduce Co 2 foot print and save on energy costs. In this paper, we have presented an approach for evaluating energy efficiency metrics for any signal processing algorithm on TI's DSP and Xilinx FPGA. This evaluation of energy metrics is very much required to characterize the implementations and for quantifying the gains achieved from any energy efficient strategy. In addition, we showed that reducing execution cycles taken by signal processing algorithm effectively reduces its dynamic power consumption. As an example, FFT/IFFT algorithm, one of the critical block in OFDMA systems is considered for energy analysis.

关键词： Measurement Digital signal processing Field programmable gate arrays Power demand Baseband Computer architecture signal processing algorithms

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Efficient Sub-Pixel Interpolation And Low Power VLSI Architecture For Fractional Motion Estimation in H.264/AVC

Efficient Sub-Pixel Interpolation And Low Power VLSI Archite...

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4th International Conference on signal processing and Communication Systems (ICSPCS)/12th International Symposium on DSP and Communication Systems (DSPCS)/9th Workshop on the Internet, Telecommunications and signal processing (WTSP)

作者： Ndili, Obianuju Ogunfunmi, Tokunbo Santa Clara Univ Dept Elect Engn Santa Clara CA 95053 USA

ISBN: (纸本)9781424479078

In this paper we propose an efficient, low power algorithm and its co-designed VLSI architecture for fractional-pel motion estimation (FME) in H.264/AVC. Our fractional-pel motion estimator uses a simplified FIR filter for half-pel interpolation. Usage of this filter reduces the required number of computations and the memory size and bandwidth for half-pel interpolation. Our simulations compare our algorithm with the state-of-the-art, in terms of rate-distortion performance and computational complexity. Our VLSI architecture is prototyped on a Field Programmable System on Chip (FPSoC), comprising a Virtex-II Pro FPGA and an embedded PowerPC processor. Our results show that our algorithm on average has better rate-distortion performance, compared to previous state-of-the-art FME algorithms, while its losses compared to FME in H.264/AVC, are insignificant. Our prototyped architecture is more hardware-efficient than previous FPGA-based architectures, in terms of power consumption, throughput, area and memory utilization. We also show that its performance in terms of transistor count, throughput and power consumption, are comparable to that of state-of-the-art ASIC implementations.

关键词： ASIC implementations FIR filters FPSoC H.264/AVC VLSI Virtex-II Pro FPGA computational complexity computational complexity embedded PowerPC processor field programmable gate arrays field programmable system on chip fractional motion estimation half-pel in

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Multidimensional Exploration of Software implementations for DSP algorithms

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Journal of VLSI signal processing systems for signal, image and video technology 2000年第1期24卷 83-98页

作者： Zitzler, Eckart Teich, Jürgen Bhattacharyya, Shuvra S. Computer Engineering and Networks Laboratory (TIK) ETH Zurich Switzerland Computer Engineering (DATE) University of Paderborn Germany Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies University of Maryland College Park USA

When implementing software for programmable digital signal processors (PDSPs), the design space is defined by a complex range of constraints and optimization objectives. Three implementation metrics that are crucial in many PDSP applications are the program memory requirement (code size), data memory requirement, and execution time. This paper addresses the problem of exploring the 3-dimensional space of trade-offs that is defined by these crucial metrics. Given a software library for a target PDSP, and a dataflow-based block diagram specification of a DSP application in terms of this library, our objective in this paper is to compute a full range of Pareto-optimal solutions. For solving this multi-objective optimization problem, an evolutionary algorithm based approach is applied. We illustrate our techniques by analyzing the trade-off fronts of a practical application for a number of well-known, commercial PDSPs.

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New programmable FFT implementations for radar signal processing

New programmable FFT implementations for radar signal proces...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： D.R. Bungard L. Lau T.L. Rorabaugh MITRE Corporation Bedford MA USA

The authors have designed two high-throughput, wide-dynamic-range, real-time FFT processors for use in advanced wide-bandwidth HF radar systems. These FFTs are capable of real-time operation at continuous throughput rates greater than 2 MHz with a programmable transform length of up to 16 K points. Either 32-b fixed-point or 32-b floating-point (IEEE format) computations can be performed. An interesting result is that both FFT design approaches provide approximately the same throughput rate, are approximately the same size (250 ICs), and require less than 100 W of power.< >

关键词： Radar signal processing signal processing algorithms Computer architecture Throughput signal design Pipelines Algorithm design and analysis Dynamic range Costs Digital signal processing chips

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Novel recursive-DCT implementations: a comparative study

Novel recursive-DCT implementations: a comparative study

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IEEE International Workshop on Intelligent Data Acquisition and advanced Computing Systems: Technology and Applications

作者： S.S. Demirsoy R. Beck I. Kale A.G. Dempster Advanced DSP and VLSI Systems Department of Electronic Systems University of Westminster London UK

Reports on a new recursive discrete cosine transform (DCT) architecture that is more efficient in terms of area and power in comparison with recently published recursive DCT architectures. Our approach employs A-, B- and C-type Goertzel filters. These three different realizations of Goertzel filters, together with a multiplier-less implementation of loop multiplications, are used so as to reduce the area, the multiplier delay and undesirable transitions, and hence the power consumption. The newly proposed DCT structure has been compared with conventional recursive implementations at different transform lengths, to observe that there are potential savings both in area and power.

关键词： Discrete cosine transforms Filters Frequency Very large scale integration Computer architecture Digital signal processing Delay Energy consumption Discrete transforms Computational complexity

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The real-time implementations of AMR codec for IMT-2000 system

The real-time implementations of AMR codec for IMT-2000 syst...

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International Conference on advanced Communication Technology (ICACT)

作者： Hyung-Jung Kim Deock-Gu Jee Man-Ho Park Byung-Sik Yoon Song-In Choi Mobile A/V Research Team Electronics and Telecommunications Research Institute (ETRI) South Korea Mobile A/V Research Team Electronics and Telecommunications Research Institute (ETRI)

We present the software and hardware implementations of AMR codec for IMT-2000 system. The real-time implementations of AMR codec algorithm are achieved using TMS320C62xx DSP chip and Teak-Lite DSP core. We describe respectively efficient software schemes for coding AMR codec algorithm and hardware designs. The AMR codec is evaluated and confirmed in 3GPP test sequences, stand-alone test system and ETRI IMT-2000 prototype system

关键词： Real time systems Digital signal processing chips Hardware Speech codecs Assembly System testing GSM Software algorithms Algorithm design and analysis Software prototyping

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Area and time efficient implementations of matrix multiplication on FPGAs

Area and time efficient implementations of matrix multiplica...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Ju-wook Jang Seonil Choi V.K.K. Prasanna Electronic Engineering Sogang University Seoul South Korea Electrical Engineering-Systems University of Southern California Los Angeles CA USA

We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the previous designs and our design are 14.45, 4.93, and 2.35, respectively, for 4 /spl times/ 4 matrix multiplication. The latency of one of the previous design is 0.57 /spl mu/s, while our design takes 0.15 /spl mu/s using 18% less area. The area of our designs is smaller by 11% - 46% compared with the best known systolic designs with the same latency for the matrices of sizes 3 /spl times/ 3 - 12 /spl times/ 12. The performance improvements tend to grow with the problem size.

关键词： Field programmable gate arrays Delay Frequency signal processing algorithms signal processing Hardware Kernel Graphics Robots Image processing

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Comparisons of FIR and IIR implementations of a Subtraction-Based Stimulus Artifact Rejection Algorithm

Comparisons of FIR and IIR Implementations of a Subtraction-...

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Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Meysam Azin Hillel J. Chiel Pedram Mohseni Electrical Engineering and Computer Science Department Case Western Reserve University Cleveland OH USA Biology Department Case Western Reserve University Cleveland OH USA

Finite impulse response (FIR) and infinite impulse response (IIR) temporal filtering techniques are investigated to assess the feasibility of very-large-scale-integrated (VLSI) implementation of a subtraction-based stimulus artifact rejection (SAR) algorithm in implantable, closed-loop neuroprostheses. The two approaches are compared in terms of their system architectures, overall performances, and the associated computational costs. Pre-recorded neural data from an Aplysia californica are used to demonstrate the functionality of the proposed implementations. Digital building blocks for an FIR-based system are also simulated in a 0.18-mum CMOS technology, showing a total power consumption of <5 muW from a 1-V supply and a die area of ~1.5 mm 2 . An IIR-based system can further reduce the required power consumption and die area.

关键词： Finite impulse response filter IIR filters Blanking signal processing algorithms Filtering algorithms Very large scale integration Satellite broadcasting Computer architecture Computational efficiency CMOS technology

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Pitch detection algorithms modifications and implementations towards automated vocal analysis

Pitch detection algorithms modifications and implementations...

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IEEE International Conference on Networking, Sensing and Control

作者： Yuhong Zhang Aaron C. Elkins Jay F. Nunamaker Department of Engineering Technology Texas Southern University Houston USA The National Center for Border Security and Immigration University of Arizona Tucson USA

Discriminating between deceit and truth is a significant security challenge in a variety of situations, including border crossings, job interviews, flight passenger screenings, and police interviews. Previous research indicates that some features of vocal speech, e.g., fundamental frequency, are related to human emotion and stress levels making them applicable deception detection. This paper focuses on voice and speech feature extraction using advanced signal processing methodology. These generated speech features are used to submit data mining algorithms for classifying deception. The result of this paper is expected to be directly applied to the deception detection system.

关键词： Speech Feature extraction

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