While in most application areas digital processors can solve problems initially, in some fields their capabilities are very limited. A typical example is vision. Simple animals outperform super-computers in the realiz...
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While in most application areas digital processors can solve problems initially, in some fields their capabilities are very limited. A typical example is vision. Simple animals outperform super-computers in the realization of basic vision tasks. In order to overcome the limitations of these conventional systems, a fundamentally different array architecture is needed. This architecture is based on the new paradigm of analogic cellular (CNN) computing whose most advanced implementation is the so-called CNN universal machine (CNN-UM). Its main components are: a) parallel architecture consisting of an array of locally-connected analog processors; b) a means of storing, locally, pixel-by-pixel, the intermediate computation results, and c) stored on-chip programmability. When implemented as a mixed-signal VLSI chip, the CNN-UM is capable of image processing at rates of trillions of operations per second with very small size and low power consumption. On the other hand, when integrating the adaptive multi-sensor array in the CNN-UM, the resulting sensor+computer array offers unprecedented capabilities. This paper reviews the latest results on CMN-UM chips and systems, and outlines the envisaged roadmap for these computers.
Digital signalprocessing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent res...
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ISBN:
(纸本)9781479903573
Digital signalprocessing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent research shows that floating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difficulties associated with fixed-point arithmetic. This paper investigates the effects of simplified floating-point arithmetic applied to an FMA-based floating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overflow-related errors with inexpensive exponent-manipulation special instructions.
Continuing advances in hardware technologies are permitting the realization of increasingly sophisticated speech processingalgorithms in real‐time equipments. The availability of commercial digital signalprocessing...
Continuing advances in hardware technologies are permitting the realization of increasingly sophisticated speech processingalgorithms in real‐time equipments. The availability of commercial digital signalprocessing integrated circuit components has been especially responsible for a reduction in the size and cost of these devices. This presentation will describe the unique requirements of speech compression and speech recognition algorithms with respect to arithmetic calculations, memory, and I/O. Representative equipment designs developed at Lincoln Laboratory for realizing real‐time speech processingalgorithms will be described. These include: the Lincoln digital signal processor (LDSP), a programmable, general‐purpose ECL machine suited for real‐time evaluation of speech processingalgorithms; the advanced linear predictive coding microprocessor (ALPCM), a flexible bit‐slice processor designed for use in operational environments; and the compact linear predictive coder, a small, narrow‐band vocoder terminal based on DSP microprocessors. The application of advanced VLSI technology to meet the processing demands of large vocabulary speech recognition will be discussed, with specific focus on an approach being pursued at Lincoln Laboratory which uses wafer scale integration and restructurable VLSI technology to exploit the high level of concurrency in the recognition algorithm. [Work sponsored by the Department of the Air Force.]
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