This presentation is aimed at reviewing VLSI approaches to signalprocessing in the time and frequency domains. Rather than give a general review of the subject, we concentrate on three chips that have been at Hirst R...
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This presentation is aimed at reviewing VLSI approaches to signalprocessing in the time and frequency domains. Rather than give a general review of the subject, we concentrate on three chips that have been at Hirst Research Centre under DCVD funding. The paper describes two chips, a correlator and a convolver, which may be applied to FIR filtering. These chips are then compared with a conventional approach using a multiplier-accumulator. The paper also describes a complex multiplier chip under development for frequency domain signalprocessing.
This paper presents a wide range of algorithms and architectures for computing the 1-D and 2-D discrete wavelet transform (DWT) and the 1-D and 2-D continuous wavelet transform (CWT). The algorithms and architectures ...
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This paper presents a wide range of algorithms and architectures for computing the 1-D and 2-D discrete wavelet transform (DWT) and the 1-D and 2-D continuous wavelet transform (CWT). The algorithms and architectures presented here are independent of the size and nature of the wavelet function. New on-line algorithms are proposed for the DWT and the CWT that require significantly small storage. The proposed systolic array and the parallel filter architectures implement these on-line algorithms and are optimal both with respect to area and time (under the word-serial model). Moreover, these architectures are very regular and support single chip implementations in VLSI. The proposed SIMD architectures implement the existing pyramid and a'trous algorithms and are optimal with respect to time.
This paper explores novel techniques involving number theoretic concepts to perform real-time digital signalprocessing for high bandwidth data stream applications in digital signalprocessing. Often the arithmetic ma...
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ISBN:
(纸本)081940943X
This paper explores novel techniques involving number theoretic concepts to perform real-time digital signalprocessing for high bandwidth data stream applications in digital signalprocessing. Often the arithmetic manipulations are simple in form (cascades of additions and multiplications in a well defined structure) but the numbers of operations that have to be computed every second can be large. This paper discusses ways in which new number theoretic mapping techniques can be used to perform DSP operations by both reducing the amount of hardware involved in the circuitry and by allowing the construction of very benign architectures down to the individual cells. Such architectures can be used in aggressive VLSI/ULSI implementations. We restrict ourselves to the computation of linear filter and transform algorithms, with the inner product form, which probably account for the vast majority of digital signalprocessing functions implemented commercially.
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