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VLSI implementations OF NUMBER-THEORETIC TECHNIQUES IN signal-processing

INTEGRATION-THE VLSI JOURNAL 1993年第3期16卷 293-313页

作者： JULLIEN, GA WIGLEY, NM MILLER, WC VLSI Research Group University of Windsor Windsor Ontario Canada N9B 3P4

This paper explores novel techniques involving number theoretic concepts to perform real-time digital signal processing for high bandwidth data stream applications in Digital signal processing. For most data stream signal processing algorithms, the arithmetic manipulations are simple in form (cascades of additions and multiplications in a well defined structure) but the numbers of operations that have to be computed every second can be large. This paper discusses ways in which recently introduced number theoretic mapping techniques can be used to perform DSP operations by both reducing the amount of hardware involved in the circuitry and by allowing the construction of very benign architectures, *** the individual cells. Such architectures can be used in aggressive VLSI/ULSI implementations. We restrict ourselves to the computation of linear filter and transform algorithms, with the inner product form, which probably account for the vast majority of digital signal processing functions implemented commercially.

关键词： POLYNOMIAL RINGS RESIDUE NUMBER SYSTEMS INNER PRODUCT COMPUTATIONS BIT-LEVEL SYSTOLIC ARRAYS PIPELINED COMPUTATION VLSI signal PROCESSORS DYNAMIC LOGIC

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SCHEDULING PARALLEL implementations OF PARTITIONED ORTHOGONAL TRANSFORMATIONS

SCHEDULING PARALLEL IMPLEMENTATIONS OF PARTITIONED ORTHOGONA...

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CONF ON advanced signal processing algorithms, architectures, and implementations 3

作者： KUCHIBHOTLA, P RAO, BD Univ. of California/San Diego (United States)

ISBN: (纸本)081940943X

Orthogonal matrix transformations form an important part of matrix-based signal processing applications. Systolic arrays for computing these algorithms have been developed and the size of these arrays usually depends directly on the size of the problem. For large matrix sizes, implementing large numbers of processors in hardware is not physically feasible. In this paper, we examine two popular orthogonal transformations, Givens rotations and householder transformations (HT), from the viewpoint of realizing a fixed-size parallel processor array that can handle large data matrices. An efficient scheduling procedure is used to compute the HT on a systolic type array, its performance is compared with that of an array designed for computing the Givens method. An important conclusion resulting from the comparison is that the performance of the HT array is superior to that for the Givens method when the matrices are larger compared to the array size.

关键词： Silicon signal processing Algorithm development Matrices Parallel computing Array processing Data storage Electrochemical etching Filtering (signal processing) Lanthanum

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NEW PARALLEL implementations FOR DTW algorithms

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IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND signal processing 1990年第4期38卷 705-711页

作者： STAINHAOUER, GN CARAYANNIS, G Computer Science Division. Department of Electrical Engineering National and Technical University of Athens Athens Greece

The parallel realization of a popular dynamic time warping (DTW) algorithm is discussed. Two alternative techniques are proposed, one based on a circular array and the other using a linear array of processing elements (PEs). The architecture of each PE is defined in both cases and computational phases are outlined. The number of PEs is not restricted to be fixed. With small modifications, both of the techniques can implement DTW with any number of PEs available. The performance of the new architectures is superior to that of architectures previously reported in the literature.< >

关键词： Speech recognition Computer architecture Speech processing Testing signal processing algorithms Computational complexity Very large scale integration Multiprocessing systems Computer science

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FFT algorithms FOR PRIME TRANSFORM SIZES AND THEIR implementations ON VAX, IBM3090VF, AND IBM RS/6000

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IEEE TRANSACTIONS ON signal processing 1993年第2期41卷 638-648页

作者： LU, C COOLEY, JW TOLIMIERI, R AWARE INC CAMBRIDGEMA 02142 UNIV RHODE ISL DEPT ELECT ENGNKINGSTONRI 02881 CUNY CITY COLL DEPT ELECT ENGNNEW YORKNY 10031

Variants of the Winograd FFT algorithm for prime transform size are derived that offer options as to operational counts and arithmetic balance. Their implementations on VAX, IBM 3090 VF, and IBM RS/6000 are discussed. For processors that perform floating-point addition, floating-point multiplication, and floating-point ''multiply-add'' with the same time delay, variants of the FFT algorithm have been designed such that all floating-point multiplications can be overlapped by using ''multiply-add.'' The use of a tensor product formulation, throughout, gives a means for producing variants of algorithms matching to computer architectures.

关键词： Fast Fourier transforms Arithmetic Delay effects Algorithm design and analysis Tensile stress Computer architecture

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Space-time adaptive processing and subband array implementations

Space-time adaptive processing and subband array implementat...

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Conference on advanced signal processing algorithms architectures and implementations XIII

作者： Zhang, YM Yang, KH Amin, MG Villanova Univ Ctr Adv Commun Villanova PA 19085 USA

ISBN: (纸本)0819450782

Inter-symbol interference (ISI) and co-channel interference (CCI) are two major sources to signal impairment in mobile communications. To suppress both ISI and CCI, space-time adaptive processing (STAP) systems are shown to be effective, leading to increased capacity and improved quality of service. The high complexity and slow convergence, however, are often the hurdles in practical implementation of the STAP systems. Several subband array implementations have been proposed for STAP over the past a few years. These methods are to provide optimal or sub-optimal steady state performance with reduced implementation complexity and improved convergence performance. The purpose of this paper is to investigate the steady state performance of subband arrays with different decimation rates and to derive analytical expressions of the minimum mean square error (MMSE). The discrete Fourier transform (DFT) based subband arrays and both unconstrained and constrained weight adaptations are considered.

关键词： space-time adaptive processing subband array filter banks array processing mobile communication inter-symbol interference co-channel interference

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advanced Baseband processing algorithms, Circuits, and implementations for 5G Communication

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2017年第4期7卷 477-490页

作者： Zhang, Chuan Huang, Yuan-Hao Sheikh, Farhana Wang, Zhongfeng Southeast Univ Natl Mobile Commun Res Lab Nanjing 210096 Jiangsu Peoples R China Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan Natl Tsing Hua Univ Inst Commun Engn Hsinchu 30013 Taiwan Intel Corp Circuit Res Lab Intel Labs Hillsboro OR 97124 USA Nanjing Univ Sch Elect Sci & Engn Nanjing 210046 Jiangsu Peoples R China

The rapid emergence of 5G communications technology and standardization has seen an accelerated transfer of theoretical concepts to advanced development and implementation. Not only are 5G baseband signal processing algorithms becoming more important, but also the co-design and implementation of corresponding circuits, architectures, and platforms are becoming necessary due to rapid standardization of 5G communications. This timely overview paper introduces circuits and systems (CAS) for key enabling technologies for the new 5G era: massive MIMO, mmWave baseband systems, NOMA schemes, advanced channel coding, and so on. The state-of-the-art research progress in these areas is summarized for interested readers to initiate discussion on limitations of existing solutions and open research problems that are looking for innovative solutions, especially in the CAS area. We hope this paper can bridge the gap between the theoretical investigation and application implementation for 5G communications.

关键词： 5G baseband implementations massive MIMO mmWave precoder non-orthogonal multiple-access (NOMA) schemes channel decoders

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GPU implementations for Fast Factorizations of STAP Covariance Matrices

GPU Implementations for Fast Factorizations of STAP Covarian...

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Conference on advanced signal processing algorithms, architectures, and Implementantions XVIII

作者： Roeder, Michael Davis, Nolan Furtek, Jeremy Braunreiter, Dennis Healy, Dennis Sci Applicat Int Corp 10260 Campus Point Dr San Diego CA 92121 USA DARPA Microsyst Technol Off Arlington VA 22203 USA

ISBN: (纸本)9780819472946

One of the main goals of the STAP-BOY program has been the implementation of a, space-time adaptive processing (STAP) algorithm on graphics processing units (GPUs) with the goal of reducing the processing time. Within the context of GPU implementation, we have further developed algorithms that exploit data redundancy inherent in particular STAP applications. Integration of these algorithms with GPU architecture is of primary importance for fast algorithmic processing times. STAP algorithms involve solving a linear system in which the transformation matrix is a covariance matrix. A standard method involves estimating a covariance matrix from a data matrix, computing its Cholesky factors by one of several methods. and then solving the system by substitution. Some STAP applications have redundancy in successive data matrices from which the covariance matrices are formed. For STAP applications in which a data matrix is updated with the addition of a new data row at the bottom and the elimination of the oldest data in the top of the matrix, a sequence of data matrices have multiple rows in common. Two methods have been developed for exploiting this type of data redundancy when computing Cholesky factors. These two methods are referred to as 1) Fast QR factorizations of successive data matrices 2) Fast Cholesky factorizations of successive covariance matrices. We have developed GPU implementations of these two methods. We show that these two algorithms exhibit reduced computational complexity when compared to benchmark algorithms that do not exploit data, redundancy. More importantly, we show that when these algorithmic improvements are optimized for the GPU architecture, the processing times of a GPU implementation of these matrix factorization algorithms may be greatly improved.

关键词： Covariance cholesky QR factorization GPGPU Space Time Adaptive processing (STAP) block update CUDA thread parallelism block parallelism

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Design tradeoffs using truncated multipliers in FIR filter implementations

Design tradeoffs using truncated multipliers in FIR filter i...

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Conference on advanced signal processing algorithms, architectures and implementations XII

作者： Walters, EG Schulte, MJ Lehigh Univ Comp Sci & Engn Dept Comp Architecture & Arithmet Lab Bethlehem PA 18015 USA

ISBN: (纸本)0819445584

This paper presents a general FIR filter architecture utilizing truncated tree multipliers for computation. The average error, maximum error, and variance of error due to truncation are derived for the proposed architecture. A novel technique that reduces the average error of the filter is presented, along with equations for computing the signal-to-noise ratio of the truncation error. A software tool written in Java is described that automatically generates structural VHDL models for specific filters based on this architecture, given parameters such as the number of taps, operand lengths, number of multipliers, and number of truncated columns. We show that a 22.5 % reduction in area can be achieved for a 24-tap filter with 16-bit operands, 4 parallel multipliers, and 12 truncated columns. For this implementation, the average reduction error is only 9.18 x 10(-5) ulps, and the reduction error SNR is only 2.4 dB less than the roundoff SNR of an equivalent filter without truncation.

关键词： FIR filters truncated multipliers automatic VHDL generation computer arithmetic application-specific designs

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Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

Efficient implementations of pipelined CORDIC based IIR digi...

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SPIE Conference on advanced signal processing algorithms, architectures, and implementations VIII

作者： Ma, J Parhi, KK Hekstra, GJ Deprettere, EF Univ Minnesota Dept ECE Minneapolis MN 55455 USA

ISBN: (纸本)0819429163

CORDIC based IIR digital filters are orthogonal filters whose internal computations consist of orthogonal transformations. These filters possess desirable properties for VLSI implementations such as regularity, local connection, low sensitivity to finite word-length implementation, and elimination of limit cycles. Recently, fine-grain pipelined CORDIC based IIR digital filter architectures which can perform the filtering operations at arbitrarily high sample rates at the cost of linear increase in hardware complexity have been developed. These pipelined architectures consist of only Givens rotations and a few additions which can be mapped onto CORDIC arithmetic based processors. However, in practical applications, implementations of Givens rotations using traditional CORDIC arithmetic are quite expensive. For example, for 16 bit accuracy, using floating point data format with 16 bit mantissa and 5 bit exponent, it will require approximately 20 pairs of shift-add operations for one Givens rotation. In this paper, we propose an efficient implementation of pipelined CORDIC based IIR digital filters based on fast orthonormal mu-rotations. Using this method, the Givens rotations are approximated by angles corresponding to orthonormal mu-rotations, which are based on the idea of CORDIC and can perform rotation with minimal number of shift-add operations. We present various methods of construction for such orthonormal mu-rotations. A significant reduction (over 76%) of the number of required shift-add operations is achieved. All types of fast rotations can be implemented as a cascade of only four basic types of shift-add stages. These stages can be executed on a modified floating-point CORDIC architecture, making the pipelined filter highly suitable for VLSI implementations.

关键词： orthogonal IIR digital filters pipelining approximate rotations orthonormal mu-rotations CORDIC architecture

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RASTERIZATION THEORY, architectures, and implementations FOR A CLASS OF TWO-DIMENSIONAL PROBLEMS

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INTEGRATION-THE VLSI JOURNAL 1988年第2期6卷 179-199页

作者： LIU, WT CAVIN, RK N CAROLINA STATE UNIV DEPT ELECT & COMP ENGN RALEIGH NC 27695 USA SEMICOND RES CORP RES TRIANGLE PK NC 27709 USA

This paper first presents a theory for rasterizing the class of two-dimensional problems which include signal/image processing, computer vision, and linear algebra. The rasterization theory is steered by an isomorphism relationship between the two-dimensional shuffle exchange network (2DSE) and the two-dimensional butterfly network (2DBN). Since in real-time applications, data are often acquired in a raster scan format, it is important to develop architectures to support the raster data structure. algorithms are developed first by using 2DSE network, then transformed into 2DBN format. Rasterization architectures can be derived for the algorithms described by 2DBN format. In the PEACE project, we have been able to show that a single, fixed communication topology, namely 2DSE, provides solution times on a 2DSE parallel computing system that for many problems approach known theoretical lower bounds. Secondly, this paper presents the generic architectures and VLSI implementation examples for the rasterization structures.

关键词： Omega network butterfly network in-place algorithm two-dimensional shuffle-exchange network rasterization 2DFFT computer vision

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