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Redundant arithmetic, algorithms and implementations

INTEGRATION-THE VLSI JOURNAL 2000年第1期30卷 13-53页

作者： González, AF Mazumder, P Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing (DSP) chips, is predominantly determined by the speed of arithmetic modules like adders and multipliers. Even though redundant arithmetic algorithms produce significant improvements in performance through the elimination of carry propagation, efficient circuit implementations of these algorithms have been traditionally difficult to obtain. This work presents a survey of circuit implementations of redundant arithmetic algorithms. The described implementations are divided into three main groups: (1) conventional binary logic circuits, which encode the multivalued digits of redundant arithmetic into two or more binary digital signals;(2) current-mode multiple-valued logic circuits, which directly represent multivalued redundant digits using non-binary digital current signals;and (3) heterostructure and quantum electronic circuits. intended for very compact designs capable of operating at extremely high speeds. For each of the circuits, the operating principle is described and the main advantages and disadvantages of the approach are discussed and compared. (C) 2000 Published by Elsevier Science B.V.

关键词： redundant number systems redundant binary logic current-mode logic multiple-valued logic quantum electronic circuits

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Efficient Hardware implementations of Low Bit Depth Motion Estimation algorithms

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IEEE signal processing LETTERS 2009年第6期16卷 513-516页

作者： Celebi, Anil Urhan, Oguzhan Hamzaoglu, Ilker Erturk, Sarp Kocaeli Univ Dept Elect & Telecommun Engn Kocaeli Univ Lab Image & Signal Proc TR-41040 Kocaeli Turkey Sabanci Univ Fac Engn & Nat Sci TR-34956 Istanbul Turkey

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.

关键词： Low bit-depth motion estimation motion estimation hardware source pixel based linear arrays

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CODING algorithms AND VLSI implementations FOR DIGITAL TV AND HDTV SATELLITE BROADCASTING

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EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS 1993年第1期4卷 11-21页

作者： MUSMANN, HG PIRSCH, P University of Hanover Appelstr. 9A 3000 Hannover 1 Germany

Source coding techniques for reducing the bit rates of TV and HDTV signals are presented and discussed with respect to satellite broadcasting applications. The source coding techniques require transmission bit rates of 9 Mbit/s for a TV and 45 Mbit/s for an HDTV signal in order to provide distribution quality as required for broadcasting. Also three scalable coding schemes are outlined which allow graceful degradations at the boundary of the broadcasting service area by a transition from a HDTV to TV picture resolution. VLSI implementations of TV and HDTV decoders have been investigated in order to achieve compact and low cost realization. It is shown that the silicon area of VLSI devices can be kept small by choosing algorithms with small signal processing requirements and by taking advantage of a priori known features. VLSI architectures for the implementation of subband filters and DCT are discussed as key components.

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Exploration of Soft-Output MIMO Detector implementations on Massive Parallel Processors

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JOURNAL OF signal processing SYSTEMS FOR signal IMAGE AND VIDEO TECHNOLOGY 2011年第1期64卷 75-92页

作者： Fasthuber, Robert Li, Min Novo, David Raghavan, Praveen Van Der Perre, Liesbet Catthoor, Francky IMEC B-3001 Louvain Belgium

Emerging Software Defined Radio (SDR) baseband platforms are based on multiple processors with massive parallelism. Although the computational power of these platforms would theoretically enable SDR solutions with advanced wireless signal processing, existing work implements still rather basic algorithms. For instance, current Multiple-Input Multiple-Output (MIMO) detector implementations are typically based on simple linear hard-output and not on advanced near-Maximum Likelihood (ML) soft-output detection. However, only the latter enables to exploit the full potential of MIMO technology. In this work, we explore the feasibility of advanced soft-output near-ML MIMO detectors on massive parallel processors. Although such detectors are considered to be very challenging due to their high computational complexity, we combine architecture-friendly algorithm design, application specific instructions and instruction-level/data-level parallelism explorations to make SDR solutions feasible. We show that, by applying the proposed combination of techniques, it is possible to obtain SDR implementations which can deliver data rates that are sufficient for future wireless systems. For example, a 2 x 4 Coarse Grain Array (CGA) processor with 16-way Single Instruction Multiple Data (SIMD) can deliver 192/368 Mbps throughput for 2 x 2 64/16-QAM transmissions. Finally, we estimate the area and power consumption of the programmable solution and compare it against a traditional Application Specific Integrated Circuit (ASIC) approach. This enables us to draw conclusions from the cost perspective.

关键词： MIMO SDR SSFE LLR CGA ASIC

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Analysis and design of parallel algorithms and implementations of matrix multiplications for image and signal processing

Analysis and design of parallel algorithms and implementatio...

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IEEE Pacific RIM Conference on Communications, Computers and signal processing

作者： Yasrebi, Mehrad Browne, James C. IBM Corp Austin TX USA

Parallel matrix multiplication algorithms (based on the common data distribution formats) used in pattern recognition, image-processing, and signal-processing applications are discussed. A novel algorithm is introduced and is shown to be the fastest one for a determined class of applications. The algorithms are analyzed for performance as a function of array dimension, data distribution formats, and the architecture of the computer upon which the algorithms are executed. Performance bounds and speedups (linear in the number of processors) are established. The results of the analysis are given both as characterizations of executions on selected classes of architectures and also in the form of theorems which establish the relative performance of the algorithms across classes of data distributions and architectures.

关键词： signal processing

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VHDL-based implementations of area and power efficient filter architectures 10

VHDL-based implementations of area and power efficient filte...

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2000 10th European signal processing Conference, EUSIPCO 2000

作者： Saastamoinen, Ilkka Saramaki, Tapio Vainio, Olii Dept. of Information Technology Tampere University of Technology P.O. Box 553 Tampere Finland

ISBN: (纸本)9789521504433

Digital signal processing operations, e.g., digital filters, are one important class of application in communication devices. A digital filtering algorithm can be implemented in various ways by selecting one architecture from the set of possible realizations. By choosing an advanced architecture notable advantages in both the silicon area and power dissipation can be achieved compared to the conventional direct-form realization. This paper focuses on interpolated finite impulse response (interpolated FIR) filter and recursive running-sum (RRS) filter based architectures. The VHDL-based implementations prove that these advanced architectures are efficient when low-power or low-area characteristics are desired. Over 55 percent savings in the area and in the power dissipation were achieved when an FIR filter with a narrow transition band was implemented using these architectures. © 2000 EUSIPCO.

关键词： FIR filters

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Efficient Hardware architectures and implementations of Packet-Level Erasure Coding Schemes for High Data Rate Reliable Satellite Communications

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2022年第3期58卷 2269-2280页

作者： Theodoropoulos, Dimitris Kranitis, Nektarios Tsigkanos, Antonis Machairas, Elias Paschalis, Antonios Natl & Kapodistrian Univ Athens Dept Informat & Telecommun Athens 15784 Greece Natl & Kapodistrian Univ Athens Dept Aerosp Sci & Technol Evripos Univ Complex NKUA Athens 34400 Greece

Forward error correction coding schemes have been used extensively in order to provide continuous and reliable telemetry data transfer from satellites to ground stations and guarantee reliable communications even at low signal-to-noise ratio regimes, where burst errors are dominant. Nevertheless, conventional bit-level channel coding can fail to provide downlink reliability against long error bursts in future high data rate radio frequency and optical (laser) links, especially when automatic repeat queuing strategies are either problematic or impossible due to specific service delay constraints. Packet-level erasure coding has been considered by the Consultative Committee for Space Data Systems (CCSDS) in CCSDS 131.5-O-1 experimental specification for application in high data rate near-earth and deep-space communications, since it can protect against long error bursts as they may come along with the effect of scintillation outages or transmission errors. implementations of packet-level encoding and decoding so far exist only in software, running on a general-purpose CPU. In this article, we introduce and compare analytical descriptions of packet-level encoding algorithms suitable for hardware implementations. Based on these algorithmic descriptions, we introduce, for the first time, architectures for hardware acceleration of these functions that allow integration on a high-speed on-board data-processing chain with very low footprint. We validate our hardware implementations and demonstrate the efficiency of the proposed architectures on a Xilinx KCU105 development board, which is built around the commercial equivalent of a space-grade field-programmable gate array device. Apart from offloading packet-level encoding from the on-board embedded processor, the proposed accelerators achieve a significant speedup (over 80 times), when compared with on-board software implementations, by porting on some of the most commonly used and state-of-the-art space-qualified embedded

关键词： Codes Encoding Parity check codes Software Field programmable gate arrays Standards Forward error correction Encoding error correction coding field-programmable gate arrays (FPGAs) forward error correction (FEC) satellite communication on-board systems

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ADAPTIVE LATTICE FILTER implementations ON PIPELINED MULTIPROCESSOR architectures.

ADAPTIVE LATTICE FILTER IMPLEMENTATIONS ON PIPELINED MULTIPR...

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ICASSP '88: 1988 International Conference on Acoustics, Speech, and signal processing. V 1, Speech processing;v 2, Multidimensional signal processing;v 3, Digital signal processing;v 4, VLSI Spectral Estimation;v 5, Audio & Electroacoustics

作者： Meyer, Martin D. Agrawal, Dharma P. North Carolina State Univ Raleigh NC USA North Carolina State Univ Raleigh NC USA

Three pipelined multiprocessor implmentations of adaptive lattice filters are examined. The three multiprocessor architectures, which can be characterized as a serial pipeline, a ladder-connected dual pipeline, and a ring pipeline, are derived directly from the computational and data-transfer requirements of adaptive lattice algorithms. The order-recursive nature of the adaptive lattice structure results in architectures which use pipelining extensively. A performance analysis is done for each multiprocessor system, with respect to two different adaptive lattice algorithms. Expressions for approximate computations time and speedup are derived for each combination of architecture and algorithm.

关键词： signal FILTERING AND PREDICTION

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Image Pattern Recognition: Algorithm implementations, Techniques, and Technology

Image Pattern Recognition: Algorithm Implementations, Techni...

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Image Pattern Recognition: Algorithm implementations, Techniques, and Technology 1987

The proceedings contain 15 papers. The topics discussed include: review of machine vision architectures;a comparison of the wire frame and mathematical morphology approaches to machine vision;normalized correlation search in alignment, gauging, and inspection;advanced image-processing architectures for machine vision;recognition methodology: algorithms TGZ architecture;an analysis of hypercube architectures for image pattern recognition algorithms;optical pattern recognition and ai algorithms and architectures for ATR and computer vision;tools for productive development of image analysis algorithms;and user interface design for a general purpose pattern recognition package.

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Modular implementations of linearly constrained beamformers

Modular implementations of linearly constrained beamformers

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advanced signal processing algorithms, architectures, and implementations II

作者： Liu, Tsung-Ching Van Veen, Barry D. Univ. of Wisconsin Madison WI USA

ISBN: (纸本)0819406945

This paper describes a cascade decomposition of the generalized sidelobe canceller (GSC) implementation for linearly constrained minimum variance beamformers. The GSC is initially separated into an adaptive interference cancellation module followed by a non-adaptive beamformer. We prove that the adaptive interference cancellation module can be decomposed into a cascade of first (or higher) order adaptive interference cancellation modules, where the order corresponds to the number of adaptive degrees of freedom represented in the module. This distributes the computational burden associated with determining the adaptive weights over several lower order problems and facilitates simultaneous implementation of beamformers with differing numbers of adaptive degrees of freedom.

关键词： signal Interference

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