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Rijndael FPGA implementations utilising look-up tables

Journal of VLSI signal processing Systems for signal, Image, and Video Technology 2003年第3期34卷 261-275页

作者： McLoone, Máire McCanny, John V. DSiPtrade Laboratories Sch. of Elec. and Electronic Eng. Queen's University of Belfast Belfast United Kingdom

This paper presents single-chip FPGA Rijndael algorithm implementations of the advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. In this paper, a Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs. A LUT-based fully pipelined Rijndael implementation is described which has a pre-placement performance of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design in which look-up tables are utilised to implement only one of the Round function transformations, and 6 times faster than other previous single-chip implementations. Iterative Rijndael implementations based on the Look-Up-Table design approach are also discussed and prove faster than typical iterative implementations.

关键词： algorithms

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Benchmarking JPEG 2000 implementations on modern CPU and GPU architectures

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JOURNAL OF COMPUTATIONAL SCIENCE 2014年第2期5卷 90-98页

作者： Ciznicki, Milosz Kierzynka, Michal Kopta, Piotr Kurowski, Krzysztof Gepner, Pawel Poznan Supercomp & Networking Ctr Noskowskiego 10 St PL-61704 Poznan Poland Intel Corp Swindon SN3 1RJ Wilts England

The use of graphics hardware for non-graphics applications has become popular among many scientific programmers and researchers as we have observed a higher rate of theoretical performance increase than the CPUs in recent years. However, performance gains may be easily lost in the context of a specific parallel application due to various both hardware and software factors. JPEG 2000 is a complex standard for data compression and coding, that provides many advanced capabilities demanded by more specialized applications. There are several JPEG 2000 implementations that utilize emerging parallel architectures with the built-in support for parallelism at different levels. Unfortunately, many available implementations are only optimized for a certain parallel architecture or they do not take advantage of recent capabilities provided by modern hardware and low level APIs. Thus, the main aim of this paper is to present a comprehensive real performance analysis of JPEG 2000. It consists of a chain of data and compute intensive tasks that can be treated as good examples of software benchmarks for modern parallel hardware architectures. In this paper we compare achieved performance results of various JPEG 2000 implementations executed on selected architectures for different data sets to identify possible bottlenecks. We discuss also best practices and advices for parallel software development to help users to evaluate in advance and then select appropriate solutions to accelerate the execution of their applications. (C) 2013 Elsevier B.V. All rights reserved.

关键词： GPU Multi-core CPU JPEG 2000 signal processing

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Efficient Hardware implementations of Low Bit Depth Motion Estimation algorithms

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IEEE signal processing LETTERS 2009年第6期16卷 513-516页

作者： Celebi, Anil Urhan, Oguzhan Hamzaoglu, Ilker Erturk, Sarp Kocaeli Univ Dept Elect & Telecommun Engn Kocaeli Univ Lab Image & Signal Proc TR-41040 Kocaeli Turkey Sabanci Univ Fac Engn & Nat Sci TR-34956 Istanbul Turkey

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.

关键词： Low bit-depth motion estimation motion estimation hardware source pixel based linear arrays

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Redundant arithmetic, algorithms and implementations

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INTEGRATION-THE VLSI JOURNAL 2000年第1期30卷 13-53页

作者： González, AF Mazumder, P Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing (DSP) chips, is predominantly determined by the speed of arithmetic modules like adders and multipliers. Even though redundant arithmetic algorithms produce significant improvements in performance through the elimination of carry propagation, efficient circuit implementations of these algorithms have been traditionally difficult to obtain. This work presents a survey of circuit implementations of redundant arithmetic algorithms. The described implementations are divided into three main groups: (1) conventional binary logic circuits, which encode the multivalued digits of redundant arithmetic into two or more binary digital signals;(2) current-mode multiple-valued logic circuits, which directly represent multivalued redundant digits using non-binary digital current signals;and (3) heterostructure and quantum electronic circuits. intended for very compact designs capable of operating at extremely high speeds. For each of the circuits, the operating principle is described and the main advantages and disadvantages of the approach are discussed and compared. (C) 2000 Published by Elsevier Science B.V.

关键词： redundant number systems redundant binary logic current-mode logic multiple-valued logic quantum electronic circuits

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Hardware implementations of computer-generated holography: a review

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OPTICAL ENGINEERING 2020年第10期59卷

作者： Wang, Youchao Dong, Daoming Christopher, Peter J. Kadis, Andrew Mouthaan, Ralf Yang, Fan Wilkinson, Timothy D. Univ Cambridge Ctr Mol Mat Photon & Elect Dept Engn Cambridge England

Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations. (C) 2020 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： computer-generated holography central processing unit graphics processing unit field-programmable gate array digital signal processor hardware accelerator holography system-on-chip

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VHDL-based implementations of area and power efficient filter architectures 10

VHDL-based implementations of area and power efficient filte...

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2000 10th European signal processing Conference, EUSIPCO 2000

作者： Saastamoinen, Ilkka Saramaki, Tapio Vainio, Olii Dept. of Information Technology Tampere University of Technology P.O. Box 553 Tampere Finland

ISBN: (纸本)9789521504433

Digital signal processing operations, e.g., digital filters, are one important class of application in communication devices. A digital filtering algorithm can be implemented in various ways by selecting one architecture from the set of possible realizations. By choosing an advanced architecture notable advantages in both the silicon area and power dissipation can be achieved compared to the conventional direct-form realization. This paper focuses on interpolated finite impulse response (interpolated FIR) filter and recursive running-sum (RRS) filter based architectures. The VHDL-based implementations prove that these advanced architectures are efficient when low-power or low-area characteristics are desired. Over 55 percent savings in the area and in the power dissipation were achieved when an FIR filter with a narrow transition band was implemented using these architectures. © 2000 EUSIPCO.

关键词： FIR filters

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Analysis and design of parallel algorithms and implementations of matrix multiplications for image and signal processing

Analysis and design of parallel algorithms and implementatio...

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IEEE Pacific RIM Conference on Communications, Computers and signal processing

作者： Yasrebi, Mehrad Browne, James C. IBM Corp Austin TX USA

Parallel matrix multiplication algorithms (based on the common data distribution formats) used in pattern recognition, image-processing, and signal-processing applications are discussed. A novel algorithm is introduced and is shown to be the fastest one for a determined class of applications. The algorithms are analyzed for performance as a function of array dimension, data distribution formats, and the architecture of the computer upon which the algorithms are executed. Performance bounds and speedups (linear in the number of processors) are established. The results of the analysis are given both as characterizations of executions on selected classes of architectures and also in the form of theorems which establish the relative performance of the algorithms across classes of data distributions and architectures.

关键词： signal processing

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Efficient Hardware architectures and implementations of Packet-Level Erasure Coding Schemes for High Data Rate Reliable Satellite Communications

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2022年第3期58卷 2269-2280页

作者： Theodoropoulos, Dimitris Kranitis, Nektarios Tsigkanos, Antonis Machairas, Elias Paschalis, Antonios Natl & Kapodistrian Univ Athens Dept Informat & Telecommun Athens 15784 Greece Natl & Kapodistrian Univ Athens Dept Aerosp Sci & Technol Evripos Univ Complex NKUA Athens 34400 Greece

Forward error correction coding schemes have been used extensively in order to provide continuous and reliable telemetry data transfer from satellites to ground stations and guarantee reliable communications even at low signal-to-noise ratio regimes, where burst errors are dominant. Nevertheless, conventional bit-level channel coding can fail to provide downlink reliability against long error bursts in future high data rate radio frequency and optical (laser) links, especially when automatic repeat queuing strategies are either problematic or impossible due to specific service delay constraints. Packet-level erasure coding has been considered by the Consultative Committee for Space Data Systems (CCSDS) in CCSDS 131.5-O-1 experimental specification for application in high data rate near-earth and deep-space communications, since it can protect against long error bursts as they may come along with the effect of scintillation outages or transmission errors. implementations of packet-level encoding and decoding so far exist only in software, running on a general-purpose CPU. In this article, we introduce and compare analytical descriptions of packet-level encoding algorithms suitable for hardware implementations. Based on these algorithmic descriptions, we introduce, for the first time, architectures for hardware acceleration of these functions that allow integration on a high-speed on-board data-processing chain with very low footprint. We validate our hardware implementations and demonstrate the efficiency of the proposed architectures on a Xilinx KCU105 development board, which is built around the commercial equivalent of a space-grade field-programmable gate array device. Apart from offloading packet-level encoding from the on-board embedded processor, the proposed accelerators achieve a significant speedup (over 80 times), when compared with on-board software implementations, by porting on some of the most commonly used and state-of-the-art space-qualified embedded

关键词： Codes Encoding Parity check codes Software Field programmable gate arrays Standards Forward error correction Encoding error correction coding field-programmable gate arrays (FPGAs) forward error correction (FEC) satellite communication on-board systems

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ADAPTIVE LATTICE FILTER implementations ON PIPELINED MULTIPROCESSOR architectures.

ADAPTIVE LATTICE FILTER IMPLEMENTATIONS ON PIPELINED MULTIPR...

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ICASSP '88: 1988 International Conference on Acoustics, Speech, and signal processing. V 1, Speech processing;v 2, Multidimensional signal processing;v 3, Digital signal processing;v 4, VLSI Spectral Estimation;v 5, Audio & Electroacoustics

作者： Meyer, Martin D. Agrawal, Dharma P. North Carolina State Univ Raleigh NC USA North Carolina State Univ Raleigh NC USA

Three pipelined multiprocessor implmentations of adaptive lattice filters are examined. The three multiprocessor architectures, which can be characterized as a serial pipeline, a ladder-connected dual pipeline, and a ring pipeline, are derived directly from the computational and data-transfer requirements of adaptive lattice algorithms. The order-recursive nature of the adaptive lattice structure results in architectures which use pipelining extensively. A performance analysis is done for each multiprocessor system, with respect to two different adaptive lattice algorithms. Expressions for approximate computations time and speedup are derived for each combination of architecture and algorithm.

关键词： signal FILTERING AND PREDICTION

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Modular implementations of linearly constrained beamformers

Modular implementations of linearly constrained beamformers

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advanced signal processing algorithms, architectures, and implementations II

作者： Liu, Tsung-Ching Van Veen, Barry D. Univ. of Wisconsin Madison WI USA

ISBN: (纸本)0819406945

This paper describes a cascade decomposition of the generalized sidelobe canceller (GSC) implementation for linearly constrained minimum variance beamformers. The GSC is initially separated into an adaptive interference cancellation module followed by a non-adaptive beamformer. We prove that the adaptive interference cancellation module can be decomposed into a cascade of first (or higher) order adaptive interference cancellation modules, where the order corresponds to the number of adaptive degrees of freedom represented in the module. This distributes the computational burden associated with determining the adaptive weights over several lower order problems and facilitates simultaneous implementation of beamformers with differing numbers of adaptive degrees of freedom.

关键词： signal Interference

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