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检索条件"任意字段=Advanced Signal-Processing Algorithms, Architectures, and Implementations"

共 154 条记录，以下是61-70 订阅

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Discrete implementations of scale transform

Discrete implementations of scale transform

引用

Proceedings of the 1999 advanced signal processing algorithms, architectures, and implementations IX

作者： Djurdjanovic, Dragan Williams, William J. Koh, Christopher K.H. Nanyang Technological Univ Singapore

Scale as a physical quantity is a recently developed concept. The scale transform can be viewed as a special case of the more general Mellin transform and its mathematical properties are very applicable in the analysis and interpretation of the signals subject to scale changes. A number of single-dimensional applications of scale concept have been made in speech analysis, processing of biological signals, machine vibration analysis and other areas. Recently, the scale transform was also applied in multi-dimensional signal processing and used for image filtering and denoising. Discrete implementation of the scale transform can be carried out using logarithmic sampling and the well-known fast Fourier transform. Nevertheless, in the case of the uniformly sampled signals, this implementation involves resampling. An algorithm not involving resampling of the uniformly sampled signals has been derived too. In this paper, a modification of the later algorithm for discrete implementation of the direct scale transform is presented. In addition, similar concept was used to improve a recently introduced discrete implementation of the inverse scale transform. Estimation of the absolute discretisation errors showed that the modified algorithms have a desirable property of yielding a smaller region of possible error magnitudes. Experimental results are obtained using artificial signals as well as signals evoked from the temporomandibular joint. In addition, discrete implementations for the separable two-dimensional direct and inverse scale transforms are derived. Experiments with image restoration and scaling through two-dimensional scale domain using the novel implementation of the separable two-dimensional scale transform pair are presented.

关键词： signal processing

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Efficient implementations of ultrasound color doppler algorithms on VLIW architectures

Efficient implementations of ultrasound color doppler algori...

引用

Medical Imaging 2009: Ultrasonic Imaging and signal processing

作者： Dasgupta, Udayan P. Magee, David Ali, Murtaza DSP Solutions R and D Center Texas Instruments Inc. 12500 TI Boulevard Dallas TX 75243 United States

ISBN: (纸本)9780819475169

DSP chips are gaining importance in ultrasound applications as the need for portability and low power grows. One of the more computationally demanding applications for ultrasound involves estimating blood flow characteristics using Doppler techniques. This ultrasound mode, called color Doppler ultrasound, is used to diagnose many conditions like blood clots, valve defects and blocked arteries. This work looks at mapping some typical color Doppler algorithms onto Texas Instruments' (TI's) high performance C64x+(tm) core. The algorithms include RF demodulation, wall filtering and flow power, velocity and turbulence estimation. This paper starts with a general technique for analyzing algorithm complexity in terms of CPU instruction cycles on VLIW architectures like the C64x+(tm). It then applies this technique to Doppler processing algorithms, explains their mapping to the C64x+(tm) architecture and derives lower bounds for the computational complexity for these algorithm kernels. For each of these algorithms, these estimates are finally compared to actual implementations, and various implementation tradeoffs will be illustrated. Based on these implementations, it will be shown that these algorithms can run on TI's C64x+(tm) based DSPs using a fraction of the available processing power. © 2009 SPIE.

关键词： Ultrasonic imaging

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Automatic generation of implementations for DSP transforms on fused multiply-add architectures

Automatic generation of implementations for DSP transforms o...

引用

IEEE International Conference on Acoustics, Speech, and signal processing

作者： Voronenko, Y Püschel, M Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

Many modern computer architectures feature fused multiply-add (FMA) instructions, which offer potentially faster performance for numerical applications. For DSP transforms, compilers can only generate FMA code to a very limited extent because optimal use of FMAs requires modifying the chosen algorithm. In this paper we present a framework for automatically generating FMA code for every linear DSP transform, which we implemented as an extension to the SPIRAL code generation system. We show that for many transforms and transform sizes, our generated FMA code matches the best-known hand-derived FMA algorithms in terms of arithmetic cost. Further, we present actual runtime results that show the speed-up obtained by using FMA instructions.

关键词： Computer architecture

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GPU-based implementations of MM algorithms. Application to Spectroscopy signal Restoration 29

GPU-based Implementations of MM Algorithms. Application to S...

引用

29th European signal processing Conference (EUSIPCO)

作者： Gharbi, Mouna Chouzenoux, Emilie Pesquet, Jean-Christophe Duval, Laurent Univ Paris Saclay INRIA Cent Supelec CVN Gif Sur Yvette France IFP Energies Nouvelles Rueil Malmaison France

ISBN: (纸本)9789082797060

Restoration of analytical chemistry data from degraded physical acquisitions is an important task for chemists to obtain accurate component analysis and sound interpretation. The high-dimensional nature of these signals and the large amount of data to be processed call for fast and efficient reconstruction methods. Existing works have primarily relied on optimization algorithms to solve a penalized formulation. Although very powerful, such methods can be computationally heavy, and hyperparameter tuning can be a tedious task for non-experts. Another family of approaches explored recently consists in adopting deep learning to perform the signal recovery task in a supervised fashion. Although fast, thanks to their formulations amenable to GPU implementations, these methods usually need large annotated databases and are not explainable. In this work, we propose to combine the best of both worlds, by proposing unfolded Majorization-Minimization (MM) algorithms with the aim to reach fast and accurate methods for sparse spectroscopy signal restoration. Two state-of-the-art iterative MM algorithms are unfolded onto deep network architectures. This allows both the deployment of GPU-friendly tools for accelerated implementation, as well as the introduction of a supervised learning strategy for tuning automatically the regularization parameter. The effectiveness of our approach is demonstrated on the restoration of a large dataset of realistic mass spectrometry data.

关键词： Majorization-Minimization subspace acceleration unfolding regularization parameter GPU mass spectrometry

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architectures and implementations of low-density parity check decoding algorithms

Architectures and implementations of low-density parity chec...

引用

45th Midwest Symposium on Circuits and Systems (MWSCAS 2002)

作者： Yeo, E Nikolic, B Anantharam, V Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

architectures for low-density parity-check (LDPC) decoders are discussed, with methods to reduce their complexity. Serial implementations similar to traditional microprocessor datapaths are compared against implementations with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Several classes of LDPC codes, such as those based on irregular random graphs and geometric properties of finite fields are evaluated in terms of their suitability for VLSI implementation and performance as measured by bit-error rate. Efficient realizations of low-density parity check decoders under area, power, and throughput constraints are of particular interest in the design of communications receivers.

关键词： signal encoding

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FPGA Based Hardware architectures for Iterative algorithms implementations

FPGA Based Hardware Architectures for Iterative Algorithms I...

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36th International Conference on Telecommunications and signal processing (TSP)

作者： Belean, Bogdan Borda, Monica Bot, Adrian Natl Inst Res & Dev Isotop & Mol Technol Dept Mass Spectrometry 65-103 Donath Cluj Napoca 400293 Romania Univ Technol Clurj Napoea Dept Commun Cluj Napoca 400609 Romania

ISBN: (纸本)9781479904020;9781479904037

The paper describes the FPGA technology together with its possibility to exploit spatial and temporal parallelism in order to implement hardware architectures for iterative algorithms. The development of hardware architecture using FPGA technology represents a reliable solution in case of various applications where fast processing in case of iterative algorithms it's mandatory. Two applications are presented where the FPGA technology is used for processing. Thus, on one hand, automatic microarray grid alignment is performed using FPGA based hardware architecture, while on the other hand, an FPGA based LDPC decoder implementation is proposed in order to improve the decoder throughput compared to state of the art approaches.

关键词： FPGA technology Low Density Parity Check Codes image processing iterative algorithms

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RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC dec...

引用

Conference on Design and architectures for signal and Image processing

作者： Bezati, Endri Mattavelli, Marco Raulet, Mickaël Ecole Polytechnique Fédérale de Lausanne CH-1015 Lausanne Switzerland IETR INSA Rennes F-35708 Rennes France

ISBN: (纸本)9781424487356

This paper describes the implementation of the MPEG AVC CABAC entropy decoder using the RVC-CAL dataflow programming language. CABAC is the Context based Adaptive Binary Arithmetic Coding entropy decoder that is used by the MPEG AVC/H.264 main and high profile video standard. CABAC algorithm provides increased compression efficiency, however presents a higher complexity compared to other entropy coding algorithms. This implementation of the CABAC entropy decoder using RVC-CAL proofs that complex algorithms can be implemented using a high level design language. This paper analyzes in detail two possible methods of implementing the CABAC entropy decoder in the dataflow paradigm. © 2010 IEEE.

关键词： Binary codes

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AN EFFICIENT ARCHITECTURE FOR HARDWARE implementations OF IMAGE processing algorithms

AN EFFICIENT ARCHITECTURE FOR HARDWARE IMPLEMENTATIONS OF IM...

引用

IEEE Symposium on Computational Intelligence in Image and signal processing

作者： Khalvati, Farzad Tizhoosh, Hamid R. Univ Waterloo Dept Syst Design Engn Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781424427604

This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy. We implement window memoization as a 2-wide superscalar pipeline such that it consumes significantly less area than conventional 2-wide superscalar pipelines. As a case study, we have applied window memoization to Kirsch edge detector. The average speedup factor was 1.76 with only 25% extra hardware.

关键词： Pipelines

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Efficient Parallel implementations of Controlled Optimization of Traffic Phases

Efficient Parallel Implementations of Controlled Optimizatio...

引用

11th International Conference on algorithms and architectures for Parallel processing (ICA3PP)

作者： Samra, Sameh El-Mahdy, Ahmed Gomaa, Walid Wada, Yasutaka Shoukry, Amin E JUST Alexandria Egypt Waseda Univ Fac Engn Sci Tokyo Japan

ISBN: (纸本)9783642246494

Finding optimal phase durations for a controlled intersection is a computationally intensive task requiring O(N-3) operations. In this paper we introduce cost-optimal parallelization of a dynamic programming algorithm that reduces the complexity to O(N-2). Three implementations that span a wide range of parallel hardware are developed. The first is based on shared-memory architecture, using the OpenMP programming model. The second implementation is based on message passing, targeting massively parallel machines including high performance clusters, and supercomputers. The third implementation is based on the data parallel programming model mapped on Graphics processing Units (GPUs). Key optimizations include loop reversal, communication pruning, load-balancing, and efficient thread to processors assignment. Experiments have been conducted on 8-core server, IBM BlueGene/L supercomputer 2-node boards with 128 processors, and GPU GTX470 GeForce Nvidia with 448 cores. Results indicate practical scalability on all platforms, with maximum speed up reaching 76x for the GTX470.

关键词： parallel processing high performance computation traffic phases

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On Elliptic Curve Cryptography implementations and evaluation 2

On Elliptic Curve Cryptography implementations and evaluatio...

引用

2nd International Conference on advanced Technologies for signal and Image processing (ATSIP)

作者： Alimi, Nejmeddine Lahbib, Younes Machhout, Mohsen Tourki, Rached Univ Tunis El Manar Fac Sci Tunis El Manar Tunis 2092 Tunisia Univ Carthage Natl Engn Sch Carthage Charguia Ii Tunis 2035 Tunisia Univ Monastir Elect & Microelect Lab Monastir 5000 Tunisia

ISBN: (纸本)9781467385268

Elliptic Curve Cryptography have known, in recent years, an increasing success in security applications thanks to their advantages such as a short keys size with a high security level. Their popularity has led to various implementations in terms of algorithms, curves, coordinate systems, platforms, etc. The aim of this work is first to explore actual trends of ECC-based implementations in different platforms through a review of a number of works. Secondly, to identify and gather the criteria and corresponding metrics used to evaluate the performance of these implementations. We also propose a platform for design exploration and evaluation of ECC designs.

关键词： Elliptic Curve Cryptography software hardware ASIC FPGA evaluation performance

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