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DesignCon 2010

作者： Takach, Andres C-based Design Mentor Graphics Corporation United States OSCI's Synthesis Working Group United States

ISBN: (纸本)9781617385469

The increasing level of circuit integration is enabling the use of more complex digital signal processing algorithms in modern applications. The fast Fourier transform (FFT) is one the most widely used signal processing algorithms. There is no single hardware implementation that fits all needs and in fact higher performance FFTs are used in applications as it becomes feasible to do so. This paper presents a family of register based architectures that can be obtained from a highly parameterizable C++ specification. The size, numerical precision, radix algorithm and parallelism of both computation and I/O transfers are parameterized in the specification. Optimized RTL targeted to a specific ASIC or FPGA technology can be generated from that specification using a high-level synthesis (HLS) flow. The generated RTL is then verified against the original C++ specification using an automated verification environment.

关键词： Specifications

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processing and analyzing health data in a big data context: Aspects and implementations 2nd

Processing and analyzing health data in a big data context: ...

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2nd International Conference on advanced Intelligent Systems for Sustainable Development, AI2SD 2019

作者： Slime, Khaoula Maizate, Abderrahim Hassouni, Larbi ENSEM/UH2 Casablanca Morocco

ISBN: (纸本)9783030366636

Nowadays, the development of machine learning algorithms and big data frameworks make the processing of data a major asset in different sectors. Indeed, this technology allows us to carry out in-depth analyzes of large masses of data and thus generate very useful results for decision-making. Among the sectors where this technology is used is that of health in which analysis and prevention are essential to improve the quality of health care. Our research focuses on improving the application of this technology in the health field. In this paper we will present big data aspects, give some implementations and discuss different big data architectures in healthcare sector. © Springer Nature Switzerland AG 2020.

关键词： Machine learning

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Performance and power analysis of parallelized implementations on an MPCore multiprocessor platform

Performance and power analysis of parallelized implementatio...

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2007 International Conference on Embedded Computer Systems: architectures, Modeling and Simulation, IC-SAMOS 2007

作者： Blume, H. Livonius, J.V. Rotenberg, L. Noll, T.G. Bothe, H. Brakensiek, J. Department of Electrical Engineering and Computer Systems RWTH Aachen University Schinkelstraße 2 52062 Aachen Germany Nokia Research Center Meesmannstr. 103 44807 Bochum Germany

ISBN: (纸本)1424410584

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled. ©2007 IEEE.

关键词： Digital signal processing

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Active Noise Control Systems: algorithms and DSP implementations

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1995年

作者： Sen M Kuo Dennis R Morgan

ISBN: (纸本)9780471134244

From the Publisher: Active noise control (ANC) is rapidly becoming the most effective way to reduce noises that can otherwise be very difficult and expensive to control. ANC is achieved by introducing a canceling "anti-noise" wave through an appropriate array of secondary sources. When applied accurately, ANC can provide effective solutions to noise-related problems in a broad range of areas, including manufacturing and industrial operations as well as consumer products. Consequently, ANC research and development has become an important focus of both industrial applications and engineering research. Active Noise Control Systems: algorithms and DSP implementations introduces the basic concepts of ANC with an emphasis on digital signal processing (DSP) hardware and adaptive signal processing algorithms, both of which have come into prominence within the last decade. The authors emphasize the practical aspects of ANC systems by combining the principles of adaptive signal processing with both experimental results and practical implementation. Applications are cited in many fields and encompass all types of noise media, including air-acoustic, hydroacoustic, vibrations, and others. The specific implementation stressed is based on the TMS320 family of signal processors from Texas Instruments, which are the most widely used worldwide. Coverage of theory includes concise derivations and analyses of commonly used adaptive structures and algorithms for active noise control applications, which are enhanced by the inclusion of a floppy disk featuring C and assembly programs for implementing many ANC systems. Mathematical representations are employed and the source code included on the disk is in a form that is easily accessible to anyone using the book. For practicing engineers, researchers, and advanced students in signal processing, Active Noise Control Systems: algorithms and DSP implementations will serve as a comprehensive, state-of-the-art text/reference on this important

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Review of Hardware implementations of Convolution for Discrete Wavelet Transform

Review of Hardware Implementations of Convolution for Discre...

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2022 IEEE North Karnataka Subsection Flagship International Conference, NKCon 2022

作者： Ramprakash, C. Prasad, Skanda Pratyusha, R. Jayaramu, Raghu The National Institute of Engineering Department of Electronics and Communication Engineering Mysuru India

ISBN: (纸本)9781665453424

Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. This work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform (DWT). For such applications, read-only memory (ROM)-based architectures are known for their speed and performance. Two such architectures-distributed arithmetic (DA) and residue number system (RNS) are reviewed. Hardware utilization of both architectures using similar inputs and parameters on the Digilent Nexys-A7-100T field programmable gate array (FPGA) platform using Xilinx Vivado and other open-source tools are reported. Distributed arithmetic (DA) is found to be favourable for small input lengths, but residue number system (RNS) will surpass it for larger input lengths. A parallel distributed arithmetic (DA) implementation is also implemented, that offers significant computational speed-up at minimal power cost. © 2022 IEEE.

关键词： Discrete wavelet transforms

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Binary openings and closings in one pass using finite-state machines 6

Binary openings and closings in one pass using finite-state ...

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Conference on advanced signal processing algorithms, architectures, and implementations VI

作者： Waltz, FM Consultant (United States)

ISBN: (纸本)0819422347

In a series of ten papers published since 1994, a radically new technique for implementing a wide range of standard image processing operations has been presented, under the acronym SKIPSM (Separated-Kernel Image processing using finite State Machines). Key steps are: (1) the operation is separated into a row operation followed by a column operation, (2) these row and column operations are put in recursive form. That is, in a form compatible with either one-step software implementation or pipelined raster-scan hardware implementation, (3) the resulting operations are realized as FSMs (finite-state machines), and (4) these FSMs are implemented in software or in inexpensive off-the-shelf integrated circuits. Note that this technique does not require separability, in the usual sense. In this paper, the SKIPSM technique is applied to computing binary openings and closings in one pass using arbitrary binary structuring elements. Whether the resulting finite state machines are implemented in software or hardware, the result is generally much faster and/or much cheaper than conventional implementations. Furthermore, this same SKIPSM architecture is highly versatile and programmable, allowing it to be software-reconfigured to perform hundreds of other software- based or pipelined image processing operations, such a binary and grey-level morphology, the Grassfire Transform, binary and grey-level template matching, binary skeletonization, etc.

关键词： fast implementations image processing finite-state machines separability pipelining real-time inspection

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Concurrent implementations of matrix eigenvalue decomposition based on isospectral flows

Concurrent implementations of matrix eigenvalue decompositio...

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Real-Time signal processing VI 1983

作者： Ang, Peng-Huat Delosme, Jean-Marc Morf, Martin Information Systems Laboratory Electrical Engineering Department Stanford University StanfordCA94305 United States

In this paper we evaluate several techniques for solving the symmetric tridiagonal problem based on the method of isospectral flow. architectures which result from these considerations are discussed. Their advantages and disadvantages from the viewpoints of numerical accuracy and ease of implementation in VLSI are also investigated. © 1983 SPIE. All rights reserved.

关键词： Eigenvalues and eigenfunctions

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Fast algorithms for implementation of Montgomery's modular multiplication technique

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CIRCUITS SYSTEMS AND signal processing 2004年第6期23卷 463-478页

作者： Mohan, PVA ECIL Bangalore 560052 Karnataka India

In this paper, algorithms for fast implementations of Montgomery's modular multiplication algorithm are proposed. These algorithms use nonredundant multibit recoding. Two techniques, one based on multiplication followed by estimation of scaled residue and the other involving integrated multiplication with scaled residue estimation, have been considered in detail. Techniques for simplifying the computation to estimate the multiple of the modulus to be added have been described. The area and computation time requirements of the proposed techniques are estimated for a general radix in order to highlight the time-space trade-offs.

关键词： fast algorithms modular multiplication Montgomery's algorithm multibit recoding Rivest Shamir and Adleman (RSA) implementation modular exponentiation high-radix implementations very large-scale integration (VLSI) architectures

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Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

Improved parameterized efficient FPGA implementations of par...

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作者： Hasan, Sami Boussakta, Said Yakovlev, Alex School of Electrical Electronic and Computer Engineering Newcastle University NE1 7RU United Kingdom

ISBN: (纸本)9781424499908

Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. This improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6 xc6vlX130T1-1lff1156 FPGA board to achieve lower power consumption of (820 mW) and a (27%-44%) less device utilization at a maximum frequency of up to (231 MHz) using Xilinx System Generator. The improved parameterized FPGA implementation is a system-level abstraction of hardwareoriented parallel programming, as an alternative to gate-level Hardware Descriptive Language (HDL), to satisfy the high performance computation of parallel multidimensional filtering algorithms at a minimal development-to-market time. © 2011 IEEE.

关键词： Parallel programming

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Efficient Hardware implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding algorithms

Efficient Hardware Implementations of LDPC Decoders, through...

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作者： Thien Truong Nguyen Ly Universite de Cergy Pontoise

学位级别：博士

The increasing demand of massive data rates in wireless communication systems will require significantly higher processing speed of the baseband signal, as compared to conventional solutions. This is especially challenging for Forward Error Correction (FEC) mechanisms, since FEC decoding is one of the most computationally intensive baseband processing tasks, consuming a large amount of hardware resources and energy. The conventional approach to increase throughput is to use massively parallel architectures. In this context, Low-Density Parity-Check (LDPC) codes are recognized as the foremost solution, due to the intrinsic capacity of their decoders to accommodate various degrees of parallelism. They have found extensive applications in modern communication systems, due to their excellent decoding performance, high throughput capabilities, and power efficiency, and have been adopted in several recent communication standards. This thesis focuses on cost-effective, high-throughput hardware implementations of LDPC decoders, through exploiting the robustness of message-passing decoding algorithms to computing inaccuracies. It aims at providing new approaches to cost/throughput op- timizations, through the use of imprecise computing and storage mechanisms, without jeopardizing the error correction performance of the LDPC code. To do so, imprecise pro- cessing within the iterative message-passing decoder is considered in conjunction with the quantization process that provides the finite-precision information to the decoder. Thus, we first investigate a low complexity code and decoder aware quantizer, which is shown to closely approach the performance of the quantizer with decision levels optimized through exhaustive search, and then propose several imprecise designs of Min-Sum (MS)-based decoders. Proposed imprecise designs are aimed at reducing the size of the memory and interconnect blocks, which are known to dominate the overall area/delay performance of the hardware de

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