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An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA architectures 12th

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10 IPPS/SPDP 98 Workshops Held in Conjunction with the 12th international parallel Processing symposium / 9th symposium on parallel Distributed Processing

作者： Ouaiss, I Govindarajan, S Srinivasan, V Kaul, M Vemuri, R Univ Cincinnati DDEL Dept ECECS Cincinnati OH 45221 USA

ISBN: (纸本)3540643591

This paper presents an integrated design system called SPARCS (synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) for automatically partitioning and synthesizing designs for reconfigurable boards with multiple field-programmable devices (FPGAs). The SPARCS system accepts design specifications at the behavior level, in the form of task graphs. The system contains a temporal partitioning tool to temporally divide and schedule the tasks on the reconfigurable architecture, a spatial partitioning tool to map the tasks to individual FPGAs, and a high-level synthesis tool to synthesize efficient register-transfer level designs for each set of tasks destined to be downloaded on each FPGA. Commercial logic and layout synthesis tools are used to complete logic synthesis, placement, and routing for each FPGA design segment. A distinguishing feature of the SPARCS system is the tight integration of the partitioning and synthesis tools to accurately predict and control design performance and resource utilizations. This paper presents an overview of SPARCS and the various algorithms used in the system, along with a brief description of how a JPEG-like image compression algorithm is mapped to a multi-FPGA board using SPARCS.

关键词： Field programmable gate arrays (FPGA)

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A reconfigureable superimposed 2D-mesh array for channel equalization

A reconfigureable superimposed 2D-mesh array for channel equ...

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IEEE international symposium on Circuits and Systems

作者： Gay-Bellile, O Marchal, X Burns, G Vaidyanathan, K Philips Res France Architecture Microsyst & VLSI Grp Suresnes France

ISBN: (纸本)0780374487

In this paper we present a,scalable and reconfigureable mesh array of programmable processing elements. It has been designed to implement multi-standard channel estimation and equalization algorithms for broadcast digital television applications. It particularly introduces the concept of a superimposed array to speed-up the execution of an adaptive filter. This paper also discusses the array configuration and programming tools. The flexibility of this solution is demonstrated, as it simultaneously addresses the mono carrier adaptive equalizer [1] for cable transmission, as well as multi-carrier channel estimation and correction for terrestrial transmission. Gate-level synthesis results have shown that this flexibility is obtained at acceptable cost.

关键词： parallel processing systems

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Modeling for synthesis with System#

Modeling for Synthesis with System#

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26th IEEE international parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Koellner, C. Mendoza, F. Mueller-Glaser, K. D. FZI Res Ctr Informat Technol Dept Embedded Syst & Sensors Engn ESS Haid & Neu Str 10-14 D-76131 Karlsruhe Germany Karlsruhe Inst Technol Inst Informat Proc Technol D-76021 Karlsruhe Germany

ISBN: (纸本)9780769546766

While Electronic Design Automation made the shift towards system design and high-level design methods keep on emerging, there is hardly any open framework which allows researchers to quickly prototype novel synthesis algorithms. We present System#, an open source system level design framework based on C#. System# tries to bridge the productivity gap by covering modeling, simulation, code transformations and VHDL code generation in a single extensible platform. We explain how common modeling principles, such as component-based design, the separation of communication and computation, concurrent behavior and time are realized in System#. The implementation of an appropriate simulator kernel is discussed. We demonstrate the potential of code transformations by giving application examples: converting a cycle-accurate sequential specification to an explicit synthesizable finite state machine representation and IP-based design. We conclude that System# is an appropriate research and integration platform which has the potential to add value to the research community.

关键词： System-level design Reconfigurable logic Csharp Dotnet Systemsharp Design automation Very high speed integrated circuits

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Extending Force-directed Scheduling with Explicit parallel and Timed Constructs for High-level synthesis

Extending Force-directed Scheduling with Explicit Parallel a...

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IEEE 19th Annual international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Sinha, Rohit Patel, Hiren D. Univ Waterloo Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9780769543017

This work extends force-directed scheduling (FDS) to support specification constructs that express parallelism and timing behaviours. We select the FDS algorithm because it maximizes the amount of resource sharing, and it naturally supports constructs for parallelism. However, timed constructs are not supported. As a result, we propose timed FDS (TFDS) that optimizes over parallel, timed and untimed constructs. In doing so, we make the following four contributions: 1) we extend the definition of control data flow graphs (CDFGs) to define timed CDFGs (TCDFGs), 2) we define a scheduling algorithm for timed constructs called TIME, 3) we extend the definition of mobility used in FDS, and 4) we present optimizations for a composition of parallel, timed and untimed constructs to better aid FDS. We implement our extensions in a high-level synthesis framework based on the abstract state machine formalism, and we generate synthesizable VHDL. We experiment with several examples such as FIR, edge detector, and a differential equation solver, and target them onto an Altera DE2 FPGA. Some of these experiments show improvements of up to 52% in circuit area when compared to their unoptimized counterparts.

关键词： High-level synthesis Force-Directed Scheduling Timing Semantics

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Comparing signal processing hardware-synthesis methods based on the Matlab tool-chain

Comparing signal processing hardware-synthesis methods based...

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2011 6th IEEE international symposium on Electronic Design, Test and Application, DELTA 2011

作者： Zoss, Rico Habegger, Andreas Bandi, Vinzenz Goette, Josef Jacomet, Marcel Bern University of Applied Sciences HuCE-microLab CH-2501 Biel-Bienne Switzerland

ISBN: (纸本)9780769543062

Various commercial and academic tools are available for the synthesis of hardware algorithms. Focusing on signal processing algorithms, we compare efficiency, flexibility and usability of hardware synthesis approaches based on the widely used MATLAB with add-on toolboxes or 3rd-party tools. We use several designs as case studies to investigate the effect of the tool features with respect to hardware architecture and design flexibility. Special emphasis is set to the designer's freedom of choice between different arithmetic operator architectures, between pipe-lining versus operator sequencing, and between parallel versus sequential architectures. © 2011 IEEE.

关键词： Simulink

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Proceedings - 2022 IEEE 36th international parallel and Distributed Processing symposium Workshops, IPDPSW 2022

Proceedings - 2022 IEEE 36th International Parallel and Dist...

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36th IEEE international parallel and Distributed Processing symposium Workshops, IPDPSW 2022

ISBN: (纸本)9781665497473

The proceedings contain 148 papers. The topics discussed include: heterogeneous architecture for sparse data processing;combined application of approximate computing techniques in DNN hardware accelerators;highly efficient ALLTOALL and ALLTOALLV communication algorithms for GPU systems;implementing spatio-temporal graph convolutional networks on graphcore IPUs;the best of many worlds: scheduling machine learning inference on CPU-GPU integrated architectures;online learning RTL synthesis for automated design space exploration;machine learning aided hardware resource estimation for FPGA DNN implementations;optimal schedules for high-level programming environments on FPGAs with constraint programming;on how to push efficient medical semantic segmentation to the edge: the SENECA approach;and exploiting high-bandwidth memory for FPGA-acceleration of inference on sum-product networks.

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Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

Reducing the Energy Cost of Irregular Code Bases in Soft Pro...

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IEEE 19th Annual international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Arora, Manish Sampson, Jack Goulding-Hotta, Nathan Babb, Jonathan Venkatesh, Ganesh Taylor, Michael Bedford Swanson, Steven Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9780769543017

This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism. Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5x for the code they target and 2.8x for whole applications.

关键词： Accelerator architectures Reconfigurable architectures Energy efficiency High level synthesis

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EXPERIMENTS WITH THE HI-PASS DSP synthesis SYSTEM

EXPERIMENTS WITH THE HI-PASS DSP SYNTHESIS SYSTEM

引用

international SYMP ON CIRCUITS AND SYSTEMS ( ISCAS 92 )

作者： DUNCAN, P SWAMY, S SPROUSE, S POTASZ, D JAIN, R CAMMACK, W GAFTER, N WONG, YW GASS, W UCLA Los Angeles 90024 CA United States Texas Instruments Dallas 75265 TX United States

ISBN: (纸本)0780305930

Hi-PASS is a CAD system for synthesizing maximally parallel architectures to implement real-time DSP algorithms. The target DSP applications are the class for which desired sample rates are too high for time sharing of hardware to be feasible. Hi-PASS accepts a C code description of the design to be synthesized and produces a structural description of the final design that can be fabricated using standard cells provided by the Lager IV silicon assembly system [5]. Intermediate steps in the Hi-PASS flow consist of conversion of the C code into a flowgraph, optimization of the flowgraph using heuristic searches, retiming for optimal placement of pipelining registers, and mapping of the flowgraph to a structural description. synthesis experiments carried out with Hi-PASS fall into two categories: 1) Application classes where the algorithm can be mapped onto standard functions such as FIR and IIR filters, for which dedicated functional compilers exist, and 2) Applications where the algorithm cannot be mapped to standard functional blocks, and which requires a genuine architecture synthesis approach with many levels of optimization. Results are presented for synthesis of FIR filters in the first category, for which Hi-PASS synthesizes architectures of comparable quality in terms of area and throughput to those generated by a dedicated functional compiler;and for an edge detection image processing algorithm in the second category, where Hi-PASS provides significant optimization gains. These experiments demonstrate the capabilities of Hi-PASS as a synthesis system for high performance DSP ASICs. © 1992 IEEE.

关键词： FIR filters

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A hybrid neural network/rule based architecture used as a text to phoneme transcriber

A hybrid neural network/rule based architecture used as a te...

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1994 international symposium on Speech, Image Processing and Neural Networks, ISSIPNN 1994

作者： Gubbins, P.R. Curtis, K.M. Burniston, J.D. Parallel Processing Specialist Group Department of Electrical and Electronic Engineering University of Nottingham United Kingdom

ISBN: (纸本)078031865X

A major stage in the synthesis of natural sounding speech from unrestricted text is the transcription from normalised text into sound representative code. Previously research has either concentrated on the improvement of rule based algorithms, or has used a very large scale neural network to carry out this task. A hybrid neural network and simplified rule base system has been proved to simulate the MOSFET operation more efficiently than a neural network alone. This paper describes the extension of this idea to the text to phoneme transcription problem. Optimum neural network size and configuration and rule base simplifications are investigated. © 1994 IEEE.

关键词： Signal processing

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Design and implementation of a high speed parallel architecture for ATM UNI

Design and implementation of a high speed parallel architect...

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international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Wen-Yu Tseng Chin-Chou Chen D.S.L. Wei Sy-Yen Kuo Department of Electrical Engineering National Taiwan University Taipei Taiwan School of Computer Science and Engineering University of Aizu Fukushima Japan

In this paper, a parallel architecture is proposed to support the operations described in the ITU-T Recommendation I.432 (B-ISDN user-network interface-Physical layer specification). It is rather difficult to perform their operations on a bit serial architecture at a high rate. This paper demonstrates how these tasks can be achieved by means of parallelism. First, we describe the user-network interfaces in general and their physical layer properties. Then a parallel architecture is proposed with a general translation method which converts the serial operation into the parallel one. The application of the parallel architecture on each function is also depicted and the system has been realized in hardware using CMOS technology.

关键词： parallel architectures Asynchronous transfer mode CMOS technology Bit rate B-ISDN Physical layer Network interfaces Frequency Computer science Design engineering

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