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Partially-dependent functional decomposition with applications in FPGA synthesis and mapping 97

Partially-dependent functional decomposition with applicatio...

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Proceedings of the 1997 ACM 5th international symposium on Field-Programmable Gate Arrays, FPGA

作者： Cong, Jason Hwang, Yean-Yow Univ of California Los Angeles CA United States

ISBN: (纸本)9780897918015

In this paper, we give a necessary and sufficient condition for the existence of partially-dependent functional decomposition and develop new algorithms to compute such decompositions. We apply our method to the synthesis and mapping for Xilinx XC4000 FPGA's which contain non-uniform sizes of LUT's in its architecture. We develop a new mapping algorithm named PDDMAP which uses CLB's to cover nodes on critical paths for depth minimization and uses LUT's to cover non-critical nodes for area minimization. On average, PDDMAP is able to reduce the depth by 13% with only 1% of increase in area comparing to the results by FlowMap followed by a CLB generation procedure match_4k. We also develop a post-mapping procedure named PDDSYN which resynthesizes mapping solutions to reduce the mapping area. On average, PDDSYN is able to improve PDDMAP mapping solutions by 5% in depth and 7% in CLB count, and achieves 8% smaller depth and 11% fewer CLB count comparing to FlowSyn followed by match_4k.

关键词： parallel processing systems

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Automatic Generation of Warp-Level Primitives and Atomic Instructions for Fast and Portable parallel Reduction on GPUs 2019

Automatic Generation of Warp-Level Primitives and Atomic Ins...

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17th IEEE/ACM international symposium on Code Generation and Optimization (CGO)

作者： De Gonzalo, Simon Garcia Huang, Sitao Gomez-Luna, Juan Hammond, Simon Mutlu, Onur Hwu, Wen-mei UIUC CS & Coordinated Sci Lab Champaign IL 61820 USA UIUC ECE & Coordinated Sci Lab Champaign IL USA Swiss Fed Inst Technol Comp Sci Zurich Switzerland Sandia Natl Labs Scalable Comp Architecture Livermore CA 94550 USA

ISBN: (纸本)9781728114361

Since the advent of GPU computing, GPU hardware has evolved at a fast pace. Since application performance heavily depends on the latest hardware improvements, performance portability is extremely challenging for GPU application library developers. Portability becomes even more difficult when new low-level instructions are added to the ISA (e.g., warp shuffle instructions) or the microarchitectural support for existing instructions is improved (e.g., atomic instructions). Library developers, besides re-tuning the code for new hardware features, deal with the performance portability issue by hand-writing multiple algorithm versions that leverage different instruction sets and microarchitectures. High-level programming frameworks and Domain Specific Languages (DSLs) do not typically support low-level instructions (e.g., warp shuffle and atomic instructions), so it is painful or even impossible for these programming systems to take advantage of the latest architectural improvements. In this work, we design a new set of high-level APIs and qualifiers, as well as specialized Abstract Syntax Tree (AST) transformations for high-level programming languages and DSLs. Our transformations enable warp shuffle instructions and atomic instructions (on global and shared memories) to be easily generated. We show a practical implementation of these transformations by building on Tangram, a high-level kernel synthesis framework. Using our new language and compiler extensions, we implement parallel reduction, a fundamental building block used in a wide range of algorithms. parallel reduction is representative of the performance portability challenge, as its performance heavily depends on the latest hardware improvements. We compare our synthesized parallel reduction to another high-level programming framework and a hand-written high-performance library across three generations of GPU architectures, and show up to 7.8x speedup (2x on average) over hand-written code.

关键词： Graphics processing units Programming Computer architecture Libraries Hardware DSL Microarchitecture

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An FPGA based parallel architecture for music melody matching 13

An FPGA based parallel architecture for music melody matchin...

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2013 ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA 2013

作者： Wang, Hao Liu, Jyh-Charn Department of Computer Science and Engineering Texas A and M University College Station TX 77840 United States

ISBN: (纸本)9781450318877

We propose an FPGA-based high performance parallel architecture for music retrieval through singing. The database consists of monophonic MIDI files which are modeled into strings, and the user sung query is modeled as a set of regular expressions (regexp), with consideration of possible key transpositions and tempo variations to tolerate imperfectly sung queries. An approximate regexp matching algorithm is developed to calculate the similarity between a regexp and a string, using edit distance as the metrics. The algorithm supports user sung queries starting anywhere in the database song, not necessarily from the beginning. Using the proposed formal models and algorithms, the similarity between the user sung query and each song in the database can be evaluated and the top-10 most similar results will be reported. We designed the approximate regexp matching algorithm in such way that all terms of the regexp can execute concurrently, which perfectly fits the massive parallelism provided by FPGA. The FPGA implemented melody matching engine (MME) is a parameterized modular architecture that can be reconfigured to implement different regexps by simply updating their parameter registers, and can therefore avoid the time-consuming code re-synthesis. MME also includes an on-board DDR2 memory to store the database, so that they can be read in to calculate edit distances locally on the board. This way, each MME forms a self-contained system and multiple MMEs can be clustered to increase parallel processing power, with virtually no overhead. MME is evaluated using the query corpus of ThinkIT with 355 sung files and database of 5563 MIDI files. It achieves a top-10 hit rate of 90.7% and a runtime of 19.4 seconds, averaging 54.6 milliseconds for a single query. MME achieves significant speedup over software-based systems while providing the same level of flexibility. © 2013 ACM.

关键词： Field programmable gate arrays (FPGA)

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Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Shortening design time through multiplatform simulations wit...

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20th IEEE international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Falcao, G. Owaida, M. Novo, D. Purnaprajna, M. Bellas, N. Antonopoulos, C. D. Karakonstantis, G. Burg, A. Ienne, P. Univ Coimbra Dept Elect & Comp Engn Inst Telecomunicacoes P-3000 Coimbra Portugal Ecole Polytech Fed Lausanne Switzerland

ISBN: (纸本)9780769546995

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3x faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

关键词： design space exploration simulation tools parallel computing FPGAs GPUs LDPC decoding

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High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and parallel Processing 16

High-efficiency Reconfigurable Crypto Accelerator Utilizing ...

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16th IEEE international symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

作者： Le, Vu Trung Duong Pham, Hoai Luan Tran, Thi Hong Duong, Thi Sang Nakashima, Yasuhiko Nara Inst Sci & Technol 8916-5 Takayama Cho Ikoma Nara 6300192 Japan Osaka Metropolitan Univ Osaka 5588585 Japan

ISBN: (纸本)9798350393613

In decentralized IoT ecosystems, four cryptographic algorithms, including SHA256, BLAKE256, BLAKE2s, and Chacha20, are principal to ensure data integrity and confidentiality. However, existing cryptographic hardware is often limited to supporting a single algorithm and suffers from low performance, which falls short of meeting the diverse requirements of these systems. To address these limitations, we introduce a reconfigurable crypto accelerator (RCA) that offers high flexibility, superior performance, and optimal hardware efficiency. Our RCA includes three novel optimizations, specifically, a homogeneous multi-core architecture, a register-adder sharing approach, and a multi-level pipeline scheduler. The RCA was successfully verified and implemented at the system-on-chip level on a ZCU102 FPGA. The real-time performance evaluation of the RCA, during the execution of various cryptographic algorithms, demonstrates an energy efficiency ranging from 94.3-160.4 Mbps/W, which is 3.1-10.5 times higher compared to modern CPUs. Experiments conducted on several FPGAs show that the RCA is higher flexibility while still outperforming previous works by 1.63-31.65 times in throughput and 1.04-2.76 times in area efficiency. Furthermore, in ASIC synthesis, the RCA exhibits exceptional throughput (48.79-92.16 Gbps), area efficiency (66.2-102.31 Gbps/mm2), and energy efficiency (186.22-287.8 Gbps/W), surpassing other related ASICbased works.

关键词： Multi-core Cryptography FPGA ASIC SHA256 Homogeneous

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Multilevel Granularity parallelism synthesis on FPGAs

Multilevel Granularity Parallelism Synthesis on FPGAs

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IEEE 19th Annual international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Papakonstantinou, Alexandros Liang, Yun Stratton, John A. Gururaj, Karthik Chen, Deming Hwu, Wen-Mei W. Cong, Jason Univ Illinois Elect & Comp Eng Dept Urbana IL 61801 USA Adv Digital Sci Ctr Singapore Singapore Univ Calif Los Angeles Dept Comp Sci Los Angeles CA USA

ISBN: (纸本)9780769543017

Recent progress in High-Level synthesis (HLS) techniques has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-generated RTL, involves lengthy logic synthesis and physical design flows. Moreover, mapping of different levels of coarse grained parallelism onto hardware spatial parallelism affects the final FPGA-based performance both in terms of cycles and frequency. Evaluation of the rich design space through the full implementation flow - starting with high level source code and ending with routed netlist - is prohibitive in various scientific and computing domains, thus hindering the adoption of reconfigurable computing. This work presents a framework for multilevel granularity parallelism exploration with HLS-order of efficiency. Our framework considers different granularities of parallelism for mapping CUDA kernels onto high performance FPGA-based accelerators. We leverage resource and clock period models to estimate the impact of multi-granularity parallelism extraction on execution cycles and frequency. The proposed Multilevel Granularity parallelism synthesis (ML-GPS) framework employs an efficient design space search heuristic in tandem with the estimation models as well as design layout information to derive a performance near-optimal configuration. Our experimental results demonstrate that ML-GPS can efficiently identify and generate CUDA kernel configurations that can significantly outperform previous related tools whereas it can offer competitive performance compared to software kernel execution on GPUs at a fraction of the energy cost.

关键词： FPGA High-Level Sytnthesis parallel Computing Design Space Exploration

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Universal logic modules for series-parallel functions 4

Universal logic modules for series-parallel functions

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4th ACM international symposium on Field-Programmable Gate Arrays, FPGA 1996

作者： Thakur, Shashidhar Wong, D.F. Department of Computer Sciences University of Texas at Austin United States

ISBN: (纸本)0769525768

The need for a two-way interaction between logic synthesis and FPGA logic module design has been stressed recently. Having a logic module that can implement many functions is a good idea only if one can also give a synthesis strategy that makes efficient use of this functionality. Traditionally technology mapping algorithms have been developed after the logic architecture has been designed. We follow a dual approach, by focusing on a specific technology mapping algorithm, namely the structural tree-based mapping algorithm, and designing a logic module that can be mapped efficiently by this algorithm. It is known that the tree-based mapping algorithm makes optimal use of a library of functions, each of which can be represented by a tree of AND, OR and NOT gates (seriesparallel or SP functions). We show how to design a SP function with a minimum number of inputs, that can implement all possible SP functions with a specified number of inputs. For instance, we demonstrate a 7-input SP function that can implement all 4-input SP functions. Mapping results show that, on an average, the number blocks of this function needed to map benchmark circuits is 12% less than that for Actel's ACTl logic modules. Our logic modules show a 4% improvement over ACTl, if the block count is scaled to take into account the number of transistors needed to implement different logic modules. © 1996 IEEE.

关键词： Computer circuits

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11th international symposium on Applied Reconfigurable Computing, ARC 2015

11th International Symposium on Applied Reconfigurable Compu...

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11th international symposium on Applied Reconfigurable Computing, ARC 2015

ISBN: (纸本)9783319162133

The proceedings contain 50 papers. The special focus in this conference is on architecture, Modeling, Tools, Applications, Network-on-a-Chip, Cryptography Applications and Extended Abstracts. The topics include: Reducing storage costs of reconfiguration contexts by sharing instruction memory cache blocks;a vector caching scheme for streaming FPGA SpMV accelerators;hardware synthesis from functional embedded domain-specific languages;operand-value-based modeling of dynamic energy consumption of soft processors in FPGA;a fully parallel particle filter architecture for FPGAs;Teach advanced reconfigurable architectures and tools;dynamic memory management in vivado-HLS for scalable many-accelerator architectures;place and route tools for the mitigation of single event transients on flash-based FPGAs;advanced systemC tracing and analysis framework for extra-functional properties;run-time partial reconfiguration simulation framework based on dynamically loadable components;architecture virtualization for run-time hardware multithreading on field programmable gate arrays;survey on real-time network-on-chip architectures;hardware benchmarking of cryptographic algorithms using high-level synthesis tools;an efficient and flexible FPGA implementation of a face detection system;a dynamically reconfigurable mixed analog-digital filter bank;a timing driven cycle-accurate simulation for coarse-grained reconfigurable architectures;a novel concept for adaptive signal processing on reconfigurable hardware;modular acquisition and stimulation system for timestamp-driven neuroscience experiments;DRAM row activation energy optimization for stride memory access on FPGA-based systems;acceleration of data streaming classification using reconfigurable technology;partial reconfiguration for dynamic mapping of task graphs onto 2D mesh platform and a challenge of portable and high-speed FPGA accelerator.

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Mapping a class of run-time dependencies onto regular arrays

Mapping a class of run-time dependencies onto regular arrays

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international symposium on parallel Processing

作者： G.M. Megson Department of Computing Science University of Newcastle Newcastle-upon-Tyne UK

The production of regular computations using algorithmic engineering techniques is beginning to play an important role in the synthesis of massively parallel and VLSI processor arrays. The author widens the class of algorithms that can be formally synthesized by introducing a mapping theorem for a class of algorithms with run-time dependencies. The technique is illustrated by deriving uniform recurrences for the so-called knapsack problem, the resulting systolic array is known to be optimal.< >

关键词： Runtime Timing Computer architecture Very large scale integration Difference equations Processor scheduling Control system synthesis Production Systolic arrays Solid modeling

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parallel architectures for programmable high-speed signal processing devices

Parallel architectures for programmable high-speed signal pr...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： A. Lacroix Institute of Applied physics Germany

For programmable high-speed digital signal processing devices the proper architecture has to be carefully selected according to the algorithms to be implemented. The appropriate number of arithmetic units depends on the degree of parallelism of the signal processing algorithm. The question of parallelism of algorithms is discussed. For the efficient exploitation of a given signal processor hardware, an appropriate processor schedule is necessary. In two examples different approaches for multiprocessor architectures are discussed.< >

关键词： parallel architectures Signal processing Signal processing algorithms Arithmetic Signal sampling parallel processing Hardware Bit rate Speech coding Speech synthesis

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