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共 162 条记录，以下是151-160 订阅

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Evolutionary graph generation system with transmigration capability for arithmetic circuit design

Evolutionary graph generation system with transmigration cap...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： N. Homma T. Aoki T. Higuchi Graduate School of Information Sciences Tohoku University Sendai JAPAN

ISBN: (纸本)0780366859

This paper presents a novel graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. This paper also demonstrates that the evolution process of EGG can be accelerated by a simple operation, called "transmigration", which is to import previously generated good solutions for creating the other solutions.

关键词： Circuit synthesis Signal processing algorithms Acceleration Algorithm design and analysis Digital arithmetic Logic circuits High level synthesis Libraries Encoding Tree graphs

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High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

High throughput partially-parallel irregular LDPC decoder ba...

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international symposium on VLSI Design, Automation and Test

作者： Wen Ji Xing Li Takeshi Ikenaga Satoshi Goto Graduate School of Information Production and Systems Waseda University Fukuoka Japan

ISBN: (纸本)9781424416165

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message- passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200 MHz.

关键词： Throughput Parity check codes Decoding Acceleration Iterative algorithms Error correction Sorting Pipeline processing CMOS technology Scheduling

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A hybrid neural network/rule based architecture used as a text to phoneme transcriber

A hybrid neural network/rule based architecture used as a te...

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international symposium on Speech, Image Processing and Neural Networks

作者： P.R. Gubbins K.M. Curtis J.D. Burniston Parallel Processing Specialist Group Department of Electrical and Electronic Engineering University of Nottingham UK

A major stage in the synthesis of natural sounding speech from unrestricted text is the transcription from normalised text into sound representative code. Previously research has either concentrated on the improvement of rule based algorithms, or has used a very large scale neural network to carry out this task. A hybrid neural network and simplified rule base system has been proved to simulate the MOSFET operation more efficiently than a neural network alone. This paper describes the extension of this idea to the text to phoneme transcription problem. Optimum neural network size and configuration and rule base simplifications are investigated.< >

关键词： Neural networks Speech synthesis Natural languages Dictionaries Artificial neural networks Knowledge based systems Network synthesis parallel processing Acoustical engineering Speech processing

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Experiments with the Hi-PASS DSP synthesis system

Experiments with the Hi-PASS DSP synthesis system

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： P. Duncan S. Sprouse D. Potasz R. Jain W. Cammack N. Gafter Y. Wong W. Gass Texas Instruments Dallas TX USA

Hi-PASS is a CAD system for synthesizing maximally parallel architectures to implement real-time DSP algorithms. The target DSP applications are the class for which desired sample rates are too high for time sharing of hardware to be feasible. Hi-PASS accepts a C code description of the design to be synthesized and produces a structural description of the final design that can be fabricated using standard cells provided by the Lager IV silicon assembly system. synthesis experiments carried out with Hi-PASS fall into two categories: application classes where the algorithm can be mapped onto standard functions, such as FIR and IIR filters, for which dedicated functional compilers exist, and applications where the algorithm cannot be mapped to standard functional blocks and which require a genuine architecture synthesis approach with many levels of optimization. Results for FIR filters show that Hi-PASS synthesizes architectures of comparable quality in terms of area and throughput to those generated by a dedicated functional compiler. Results for an edge detection image processing algorithm of the second category show that Hi-PASS provides significant optimization gains.< >

关键词： Digital signal processing Finite impulse response filter Design automation parallel architectures Real time systems Time sharing computer systems Hardware Code standards Silicon Assembly systems

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synthesis of Thinned Planar Arrays with Accurate Mutual Coupling Modeling

Synthesis of Thinned Planar Arrays with Accurate Mutual Coup...

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IEEE international symposium on Antennas and Propagation

作者： Lorenzo Poli A-Min Yao Erni Zhu Alessandro Polo Paolo Rocca Andrea Massa CNIT - “University of Trento” Research Unit Trento Italy Shanghai Huawei Technologies Co. Ltd. Shanghai P. R. China ELEDIA Research Center (ELEDIA@XIDIAN - Xidian University) Xi'an China ELEDIA Research Center (ELEDIA@UESTC - UESTC) Chengdu China ELEDIA Research Center (ELEDIA@TSINGHUA - Tsinghua University) Beijing China

ISBN: (纸本)9781728146713

The synthesis of thinned planar arrays of real radiating elements for 5G communications systems is addressed. A nature-inspired optimization strategy based on the Genetic Algorithm (GA) is employed for defining the simplified array architecture in order to reduce the number of transmit/receive modules and radio-frequency (RF) chains with respect to a fully-populated array architecture. For each iteration of the GA-based optimization process, the array pattern is efficiently calculated by considering a limited set of representative embedded element patterns which allow taking into account the mutual coupling phenomena and to obtain an accurate prediction of the real radiation performance. A representative numerical example is reported to validate the proposed approach.

关键词： Radio frequency Phased arrays Mutual coupling Meetings Planar arrays parallel processing Prediction algorithms

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Universal Logic Modules for Series-parallel Functions

Universal Logic Modules for Series-Parallel Functions

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Proceedings of the ACM international symposium on Field-Programmable Gate Arrays, FPGA

作者： S. Thakur D.F. Wong Department of Computer Science University of Technology Austin USA

The need for a two-way interaction between logic synthesis and FPGA logic module design has been stressed recently. Having a logic module that can implement many functions is a good idea only if one can also give a synthesis strategy that makes efficient use of this funtionality. Traditionally technology mapping algorithms have been developed after the logic architecture has been designed. We follow a dual approach, by focusing on a specific technology mapping algorithm, namely the structural tree-based mapping algorithm, and designing a logic module that can be mapped efficiently by this algorithm. It is known that the tree-based mapping algorithm makes optimal use of a library of funtions, each of which can be represented by a tree of AND, OR and NOT gates (series-parallel or SP functions). We show how to design a SP function with a minimum number of inputs, that can implement all possible SP functions with a specified number of inputs. For instance, we demonstrate a 7-input SP function that can implement all 4-input SP functions. Mapping results show that, on an average, the number blocks of this function needed to map benchmark circuits is 12% less than that for Actel's ACT1 logic modules. Our logic modules show a 4% improvement over ACT1, if the block count is scaled to take into account the number of transistors needed to implement different logic modules.

关键词： Logic arrays Field programmable gate arrays

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Automated synthesis of Target-Dependent Programs for Polynomial Evaluation in Fixed-Point Arithmetic

Automated Synthesis of Target-Dependent Programs for Polynom...

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international symposium on Symbolic and Numeric algorithms for Scientific Computing (SYNASC)

作者： Christophe Mouilleron Amine Najahi Guillaume Revy ENSIIE Évry France Univ. Perpignan Via Domitia Perpignan France CNRS Montpellier France Univ. Montpellier II Montpellier France

The design of both fast and numerically accurate programs is a real challenge. Thus, the CGPE tool was introduced to assist programmers in synthesizing fast and numerically certified codes in fixed-point arithmetic for the particular case of polynomial evaluation. For performance purposes, this tool produces programs using exclusively unsigned arithmetic and addition/subtraction or multiplication operations, thus requiring some constraints on the fixed-point operands. These choices are well-suited when dealing with the implementation of certain mathematical functions, however they prevent from tackling a broader class of polynomial evaluation problems. In this paper, we first expose a rigorous arithmetic model for CGPE that takes into account signed arithmetic. Then, in order to make the most out of advanced instructions, we enhance this tool with a multi-criteria instruction selection module. This allows us to optimize the generated codes according to different criteria, like operation count, evaluation latency, or accuracy. Finally, we illustrate this technique on operation count, and we show that it yields an average reduction of up to 22.3% of the number of operations in the synthesized codes of some functions. We also explicit practical examples to show the impact of using accuracy based rather than latency based instruction selection.

关键词： Polynomials Computer architecture Accuracy Program processors Algorithm design and analysis parallel processing Hardware

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Dynamic data flow analysis for NoC based application synthesis

Dynamic data flow analysis for NoC based application synthes...

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international Workshop on Rapid System Prototyping (RSP)

作者： Matthieu Payet Virginie Fresse Frederic Rousseau Pascal Remy Univ. de Lyon Saint-Etienne France Univ. de Saint-Etienne CNRS UMR 5516 Lab. Hubert Curien Saint-Etienne France Univ. Grenoble Alpes TIMA Laboratory Grenoble CNRS TIMA Laboratory Grenoble France ADACSYS Courbevoie France

ISBN: (纸本)9781467382779

Network-on-Chip (NoC) is an interesting communication fabric for multi processing element architectures that benefits from the parallelism of algorithms. We present a method that uses a symbolic execution technique to extract the parallelism of an application to be mapped on FPGAs using the flexibility of a NoC communication infrastructure and the properties of a high level programming language. An application specific hardware is then generated using a High Level synthesis flow. We provide a dedicated mechanism for data paths reconfiguration that allows different applications to run on the same set of processing elements. Thus, the output design is programmable and has a processor-less distributed control. This approach of using NoCs enables us to automatically design generic architectures that can be used on FPGA servers for High Performance Reconfigurable Computing. We validate our method on binomial tree applications used for option pricing on FPGAs.

关键词： Hardware Field programmable gate arrays Algorithm design and analysis Libraries parallel processing Data mining Computer architecture

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MOCHA: Morphable Locality and Compression Aware architecture for Convolutional Neural Networks

MOCHA: Morphable Locality and Compression Aware Architecture...

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international symposium on parallel and Distributed Processing (IPDPS)

作者： Syed Mohammad Asad Hassan Jafri Ahmed Hemani Kolin Paul Naeem Abbas Department of Electronics Royal Institute of Technology Stockholm Sweden Indian Institute of Technology Delhi India National University of Science and Technology Pakistan

Today, machine learning based on neural networks has become mainstream, in many application domains. A small subset of machine learning algorithms, called Convolutional Neural Networks (CNN), are considered as state-ofthe- art for many applications (e.g. video/audio classification). The main challenge in implementing the CNNs, in embedded systems, is their large computation, memory, and bandwidth requirements. To meet these demands, dedicated hardware accelerators have been proposed. Since memory is the major cost in CNNs, recent accelerators focus on reducing the memory accesses. In particular, they exploit data locality using either tiling, layer merging or intra/inter feature map parallelism to reduce the memory footprint. However, they lack the flexibility to interleave or cascade these optimizations. Moreover, most of the existing accelerators do not exploit compression that can simultaneously reduce memory requirements, increase the throughput, and enhance the energy efficiency. To tackle these limitations, we present a flexible accelerator called MOCHA. MOCHA has three features that differentiate it from the state-of-the-art: (i) the ability to compress input/ kernels, (ii) the flexibility to interleave various optimizations, and (iii) intelligence to automatically interleave and cascade the optimizations, depending on the dimension of a specific CNN layer and available resources. Post layout synthesis results reveal that MOCHA provides up to 63% higher energy efficiency, up to 42% higher throughput, and up to 30% less storage, compared to the next best accelerator, at the cost of 26-35% additional area.

关键词： Kernel Convolution Encoding Neural networks parallel processing Throughput Random access memory

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High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and parallel Processing

High-efficiency Reconfigurable Crypto Accelerator Utilizing ...

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IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Vu Trung Duong Le Hoai Luan Pham Thi Hong Tran Thi Sang Duong Yasuhiko Nakashima Nara Institute of Science and Technology Nara Japan Osaka Metropolitan University Osaka Japan

In decentralized IoT ecosystems, four cryptographic algorithms, including SHA256, BLAKE256, BLAKE2s, and Chacha20, are principal to ensure data integrity and confidentiality. However, existing cryptographic hardware is often limited to supporting a single algorithm and suffers from low performance, which falls short of meeting the diverse requirements of these systems. To address these limitations, we introduce a reconfigurable crypto accelerator (RCA) that offers high flexibility, superior performance, and optimal hardware efficiency. Our RCA includes three novel optimizations, specifically, a homogeneous multi-core architecture, a register-adder sharing approach, and a multilevel pipeline scheduler. The RCA was successfully verified and implemented at the system-on-chip level on a ZCU102 FPGA. The real-time performance evaluation of the RCA, during the execution of various cryptographic algorithms, demonstrates an energy efficiency ranging from 94.3-160.4 Mbps/W, which is 3.1-10.5 times higher compared to modern CPUs. Experiments conducted on several FPGAs show that the RCA is higher flexibility while still outperforming previous works by 1.63-31.65 times in throughput and 1.04-2.76 times in area efficiency. Furthermore, in ASIC synthesis, the RCA exhibits exceptional throughput (48.79-92.16 Gbps), area efficiency (66.2-102.31 Gbps/mm 2 ), and energy efficiency (186.22-287.8 Gbps/W), surpassing other related ASIC-based works.

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