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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Laszlo, Endre Nagy, Zoltan Giles, Michael B. Reguly, Istvan Appleyard, Jeremy Szolgay, Peter Pazmany Peter Catholic Univ Budapest Hungary Hungarian Acad Sci Inst Comp Sci & Control Budapest Hungary Univ Oxford Oxford England NVIDIA Corp Santa Clara CA USA

ISBN: (纸本)9781479983919

Common parallel computer microarchitectures offer a wide variety of solutions to implement numerical algorithms. The efficiency of different algorithms applied to the same problem vary with the underlying architecture which can be a multi-core CPU, many-core GPU, Intel's MIC (Many Integrated Core) or FPGA architecture. Significant differences between these architectures exist in the ISA (Instruction Set architecture) and the way the compute flow is executed. The way parallelism is expressed changes with the ISA, thread management and customization available on the device. These differences pose restrictions to the implementable algorithms. The aim of the work is to analyze the efficiency of the algorithms through the architectural differences. The problem at hand is the one-factor Black-Scholes option pricing equation which is a parabolic PDE solved with explicit and implicit time-marching algorithms. In the implicit solution a scalar tridiagonal system of equations needs to be solved. The possible CPU, GPU implementations along with novel FPGA solutions with HLS (High Level synthesis) will be shown. Performance is also analyzed and remarks on efficiency are made.

关键词： Efficiency

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11th international symposium on Applied Reconfigurable Computing, ARC 2015

11th International Symposium on Applied Reconfigurable Compu...

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11th international symposium on Applied Reconfigurable Computing, ARC 2015

ISBN: (纸本)9783319162133

The proceedings contain 50 papers. The special focus in this conference is on architecture, Modeling, Tools, Applications, Network-on-a-Chip, Cryptography Applications and Extended Abstracts. The topics include: Reducing storage costs of reconfiguration contexts by sharing instruction memory cache blocks;a vector caching scheme for streaming FPGA SpMV accelerators;hardware synthesis from functional embedded domain-specific languages;operand-value-based modeling of dynamic energy consumption of soft processors in FPGA;a fully parallel particle filter architecture for FPGAs;Teach advanced reconfigurable architectures and tools;dynamic memory management in vivado-HLS for scalable many-accelerator architectures;place and route tools for the mitigation of single event transients on flash-based FPGAs;advanced systemC tracing and analysis framework for extra-functional properties;run-time partial reconfiguration simulation framework based on dynamically loadable components;architecture virtualization for run-time hardware multithreading on field programmable gate arrays;survey on real-time network-on-chip architectures;hardware benchmarking of cryptographic algorithms using high-level synthesis tools;an efficient and flexible FPGA implementation of a face detection system;a dynamically reconfigurable mixed analog-digital filter bank;a timing driven cycle-accurate simulation for coarse-grained reconfigurable architectures;a novel concept for adaptive signal processing on reconfigurable hardware;modular acquisition and stimulation system for timestamp-driven neuroscience experiments;DRAM row activation energy optimization for stride memory access on FPGA-based systems;acceleration of data streaming classification using reconfigurable technology;partial reconfiguration for dynamic mapping of task graphs onto 2D mesh platform and a challenge of portable and high-speed FPGA accelerator.

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ARC 2014: A Multidimensional FPGA-Based parallel DBSCAN architecture

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2015年第1期9卷 2-2页

作者： Scicluna, Neil Bouganis, Christos-Savvas Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

Clustering large numbers of data points is a very computationally demanding task that often needs to be accelerated in order to be useful in practical applications. This work focuses on the Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm, which is one of the state-of-the-art clustering algorithms, and targets its acceleration using an FPGA device. The article presents an optimized, scalable, and parameterizable architecture that takes advantage of the internal memory structure of modern FPGAs in order to deliver a high-performance clustering system. Post-synthesis simulation results show that the developed system can obtain mean speedups of 31 x in real-world tests and 202 x in synthetic tests when compared to state-of-the-art software counterparts running on a quad-core 3.4GHz Intel i7-2600k. Additionally, this implementation is also capable of clustering data with any number of dimensions without impacting the performance.

关键词： Design algorithms Performance Clustering DBSCAN FPGA parallel hardware architectures

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Analysis of parallel Processor architectures for the Solution of the Black-Scholes PDE

Analysis of Parallel Processor Architectures for the Solutio...

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IEEE international symposium on Circuits and Systems

作者： Endre Laszlo Zoltan Nagy Michael B. Giles Istvan Reguly Jeremy Appleyard Peter Szolgay Pazmany Peter Catholic University Budapest Hungary Hungarian Academy of Sciences Institute for Computer Science and Control Budapest Hungary University of Oxford Oxford United Kingdom NVIDIA Corporation United Kingdom

ISBN: (纸本)9781479983926

关键词： architecture Processor architectures Building construction implicit solution concurrent processor algorithm efficiency algorithms System of equations central processing units Field programmable gate arrays

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Dynamic data flow analysis for NoC based application synthesis

Dynamic data flow analysis for NoC based application synthes...

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international Workshop on Rapid System Prototyping (RSP)

作者： Matthieu Payet Virginie Fresse Frederic Rousseau Pascal Remy Univ. de Lyon Saint-Etienne France Univ. de Saint-Etienne CNRS UMR 5516 Lab. Hubert Curien Saint-Etienne France Univ. Grenoble Alpes TIMA Laboratory Grenoble CNRS TIMA Laboratory Grenoble France ADACSYS Courbevoie France

ISBN: (纸本)9781467382779

Network-on-Chip (NoC) is an interesting communication fabric for multi processing element architectures that benefits from the parallelism of algorithms. We present a method that uses a symbolic execution technique to extract the parallelism of an application to be mapped on FPGAs using the flexibility of a NoC communication infrastructure and the properties of a high level programming language. An application specific hardware is then generated using a High Level synthesis flow. We provide a dedicated mechanism for data paths reconfiguration that allows different applications to run on the same set of processing elements. Thus, the output design is programmable and has a processor-less distributed control. This approach of using NoCs enables us to automatically design generic architectures that can be used on FPGA servers for High Performance Reconfigurable Computing. We validate our method on binomial tree applications used for option pricing on FPGAs.

关键词： Hardware Field programmable gate arrays Algorithm design and analysis Libraries parallel processing Data mining Computer architecture

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Automated synthesis of Target-Dependent Programs for Polynomial Evaluation in Fixed-Point Arithmetic

Automated Synthesis of Target-Dependent Programs for Polynom...

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international symposium on Symbolic and Numeric algorithms for Scientific Computing (SYNASC)

作者： Christophe Mouilleron Amine Najahi Guillaume Revy ENSIIE Évry France Univ. Perpignan Via Domitia Perpignan France CNRS Montpellier France Univ. Montpellier II Montpellier France

The design of both fast and numerically accurate programs is a real challenge. Thus, the CGPE tool was introduced to assist programmers in synthesizing fast and numerically certified codes in fixed-point arithmetic for the particular case of polynomial evaluation. For performance purposes, this tool produces programs using exclusively unsigned arithmetic and addition/subtraction or multiplication operations, thus requiring some constraints on the fixed-point operands. These choices are well-suited when dealing with the implementation of certain mathematical functions, however they prevent from tackling a broader class of polynomial evaluation problems. In this paper, we first expose a rigorous arithmetic model for CGPE that takes into account signed arithmetic. Then, in order to make the most out of advanced instructions, we enhance this tool with a multi-criteria instruction selection module. This allows us to optimize the generated codes according to different criteria, like operation count, evaluation latency, or accuracy. Finally, we illustrate this technique on operation count, and we show that it yields an average reduction of up to 22.3% of the number of operations in the synthesized codes of some functions. We also explicit practical examples to show the impact of using accuracy based rather than latency based instruction selection.

关键词： Polynomials Computer architecture Accuracy Program processors Algorithm design and analysis parallel processing Hardware

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An FPGA based parallel architecture for music melody matching 13

An FPGA based parallel architecture for music melody matchin...

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2013 ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA 2013

作者： Wang, Hao Liu, Jyh-Charn Department of Computer Science and Engineering Texas A and M University College Station TX 77840 United States

ISBN: (纸本)9781450318877

We propose an FPGA-based high performance parallel architecture for music retrieval through singing. The database consists of monophonic MIDI files which are modeled into strings, and the user sung query is modeled as a set of regular expressions (regexp), with consideration of possible key transpositions and tempo variations to tolerate imperfectly sung queries. An approximate regexp matching algorithm is developed to calculate the similarity between a regexp and a string, using edit distance as the metrics. The algorithm supports user sung queries starting anywhere in the database song, not necessarily from the beginning. Using the proposed formal models and algorithms, the similarity between the user sung query and each song in the database can be evaluated and the top-10 most similar results will be reported. We designed the approximate regexp matching algorithm in such way that all terms of the regexp can execute concurrently, which perfectly fits the massive parallelism provided by FPGA. The FPGA implemented melody matching engine (MME) is a parameterized modular architecture that can be reconfigured to implement different regexps by simply updating their parameter registers, and can therefore avoid the time-consuming code re-synthesis. MME also includes an on-board DDR2 memory to store the database, so that they can be read in to calculate edit distances locally on the board. This way, each MME forms a self-contained system and multiple MMEs can be clustered to increase parallel processing power, with virtually no overhead. MME is evaluated using the query corpus of ThinkIT with 355 sung files and database of 5563 MIDI files. It achieves a top-10 hit rate of 90.7% and a runtime of 19.4 seconds, averaging 54.6 milliseconds for a single query. MME achieves significant speedup over software-based systems while providing the same level of flexibility. © 2013 ACM.

关键词： Field programmable gate arrays (FPGA)

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Modeling for synthesis with System#

Modeling for Synthesis with System#

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26th IEEE international parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Koellner, C. Mendoza, F. Mueller-Glaser, K. D. FZI Res Ctr Informat Technol Dept Embedded Syst & Sensors Engn ESS Haid & Neu Str 10-14 D-76131 Karlsruhe Germany Karlsruhe Inst Technol Inst Informat Proc Technol D-76021 Karlsruhe Germany

ISBN: (纸本)9780769546766

While Electronic Design Automation made the shift towards system design and high-level design methods keep on emerging, there is hardly any open framework which allows researchers to quickly prototype novel synthesis algorithms. We present System#, an open source system level design framework based on C#. System# tries to bridge the productivity gap by covering modeling, simulation, code transformations and VHDL code generation in a single extensible platform. We explain how common modeling principles, such as component-based design, the separation of communication and computation, concurrent behavior and time are realized in System#. The implementation of an appropriate simulator kernel is discussed. We demonstrate the potential of code transformations by giving application examples: converting a cycle-accurate sequential specification to an explicit synthesizable finite state machine representation and IP-based design. We conclude that System# is an appropriate research and integration platform which has the potential to add value to the research community.

关键词： System-level design Reconfigurable logic Csharp Dotnet Systemsharp Design automation Very high speed integrated circuits

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Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Shortening design time through multiplatform simulations wit...

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20th IEEE international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Falcao, G. Owaida, M. Novo, D. Purnaprajna, M. Bellas, N. Antonopoulos, C. D. Karakonstantis, G. Burg, A. Ienne, P. Univ Coimbra Dept Elect & Comp Engn Inst Telecomunicacoes P-3000 Coimbra Portugal Ecole Polytech Fed Lausanne Switzerland

ISBN: (纸本)9780769546995

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3x faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

关键词： design space exploration simulation tools parallel computing FPGAs GPUs LDPC decoding

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Comparing signal processing hardware-synthesis methods based on the Matlab tool-chain

Comparing signal processing hardware-synthesis methods based...

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2011 6th IEEE international symposium on Electronic Design, Test and Application, DELTA 2011

作者： Zoss, Rico Habegger, Andreas Bandi, Vinzenz Goette, Josef Jacomet, Marcel Bern University of Applied Sciences HuCE-microLab CH-2501 Biel-Bienne Switzerland

ISBN: (纸本)9780769543062

Various commercial and academic tools are available for the synthesis of hardware algorithms. Focusing on signal processing algorithms, we compare efficiency, flexibility and usability of hardware synthesis approaches based on the widely used MATLAB with add-on toolboxes or 3rd-party tools. We use several designs as case studies to investigate the effect of the tool features with respect to hardware architecture and design flexibility. Special emphasis is set to the designer's freedom of choice between different arithmetic operator architectures, between pipe-lining versus operator sequencing, and between parallel versus sequential architectures. © 2011 IEEE.

关键词： Simulink

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