This paper compares some parallel computation schemes from view of simple usage, and proposes ADEPS as the most highly recommended. As shown, it produces simple programming language ADETRAN and also sophisticated mach...
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A massively parallel computer handles massive amount of data with simultaneous access requests from multiple processors, and therefore the massively parallel computer must have a large capacity secondary storage syste...
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ISBN:
(纸本)0818678704
A massively parallel computer handles massive amount of data with simultaneous access requests from multiple processors, and therefore the massively parallel computer must have a large capacity secondary storage system. of very high concurrency. Such a storage system should consists many disks that are connected in parallel. With, such large-scale parallel disk systems, access load balancing is extremely important to enhance the effective operation of all disks. In. this paper, we propose a parallel file access method named DECODE (Dynamic Express Changing Of Data Entry) which perform dynamic load balancing over all disks according to the load status of each disk. The DECODE can achieve load balancing by changing the disk. for writing data to the low load disk. The efficiency of this method was verified by preliminary performance evaluation using software simulation under various access conditions by changing the access pattern and the access size. And the effects of some parameters used in this method was evaluated also.
Peculiarity of the most direct algorithms for solving system of linear equations is the use of divisions for the elimination of unknowns. Division requires great time for its execution, when the multiprecision arithme...
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In this paper, a parallel and fault-tolerant LAN (P_FTLAN) with dual communication subnetworks is presented to improve LANs' reliability. Its function modes, technical characters, hardware and software architectur...
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In this paper, a parallel and fault-tolerant LAN (P_FTLAN) with dual communication subnetworks is presented to improve LANs' reliability. Its function modes, technical characters, hardware and software architectures, and some key implementation techniques, such as logical addresses and parallel mechanisms, are described in details. Our prototype system and analyzing results suggest that the scheme presented in the paper not only provides an effective approach to high reliable LANs, but also can improve their performance greatly.
The Massively parallel Processing Project started in 1992 as a priority area of research for the Ministry of Education in Japan. The objective of this research project is to establish the basic technology of massively...
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The paper proposes a new architecture, which has the potential to support low-level image processing as well as intermediate and high-level vision analysis efficiently. The integrated architecture consists of a mesh o...
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In this paper, we give efficient parallel and distributed algorithms for the topological sort problem on acyclic graphs with n vertices. Our parallel algorithm solves the problem on a CREW PRAM in O(log2n) time with O...
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In this paper, we give efficient parallel and distributed algorithms for the topological sort problem on acyclic graphs with n vertices. Our parallel algorithm solves the problem on a CREW PRAM in O(log2n) time with O(M(n)/log n) processors, where M(n) denotes the number of processors needed to multiply two n × n integer matrices over the integer ring. The best known upper bound of M(n) is O(n2.376). The parallel algorithm can also solve the problem on processor arrays with reconfigurable bus systems in O(1) time and O(n3) processors. Our distributed algorithm solves the topological sort problem of an arbitrary asynchronous network with communication complexity O(n2).
Recently, high-performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These design are complex and have frequently shown disappointing per...
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Recently, high-performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These design are complex and have frequently shown disappointing performance. A complementary approach is the use of static scheduling techniques to exploit the same parallelism. In this paper we describe some of the tradeoffs between the use of static and dynamic scheduling techniques and show that with appropriate scheduling, low-complexity designs using only static scheduling have significant advantages over high-complexity designs using dynamic scheduling in real systems.
CP-PACS (Computational Physics by parallel Array Computer System) is a massively parallel processor with 2048 Processing Units built at Center for Computational Physics, University of Tsukuba. The node processor of CP...
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CP-PACS (Computational Physics by parallel Array Computer System) is a massively parallel processor with 2048 Processing Units built at Center for Computational Physics, University of Tsukuba. The node processor of CP-PACS is a RISC microprocessor enhanced by Pseudo Vector Processing feature, which can realize high-performance vector processing. The interconnection network is 3-dimensional Hyper-Crossbar Network, which has high flexibility and embeddability for various network topologies and communication patterns. The theoretical peak performance of whole system is 614.4 GFLOPS. In this paper, we describe the overview of CP-PACS architecture and several special architectural characteristics of it. The performance evaluation on parallel LINPACK benchmark is also shown.
Currently, many parallelalgorithms are defined for shared memory architectures. The preferred machine model is the PRAM, but this model does not take into account properties of existing architectures that have a dist...
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