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Supercompilers for massively parallel architectures 1

Supercompilers for massively parallel architectures

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1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Chapman, Barbara Pantano, Mario Zima, Hans Institute for Software Technology and Parallel Systems University of Vienna Brunner Strasse 72 ViennaA-1210 Austria

ISBN: (纸本)081867038X

We describe the design of a compilation system, which translates Fortran programs automatically into explicitly parallel programs for a massively parallel architecture. Such a compiler must automatically generate data distributions and derive program transformation strategies based on a combination of heuristics and analysis features. Programs are subjected to an iterative tuning process, involving three major components: a restructuring system, a performance analysts subsystem, and a parallelization support environment. Many of the components in this environment have already been implemented in the framework of the Vienna Fortran compilation system. © 1995 IEEE.

关键词： parallel architectures

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Software engineering techniques and tools for high performance parallel systems 1

Software engineering techniques and tools for high performan...

引用

1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Croll, Peter R. Jelly, Innes Gorton, Ian Department of Computer Science University of Sheffield United Kingdom Computing Research Centre Sheffield Hallam University United Kingdom Department of Computer Science University of New South Wales Australia

ISBN: (纸本)081867038X

This paper considers the current state of software engineering for parallel systems. A review of existing approaches and techniques identifies inadequacies. Recent work on design, verification and automated support is outlined. The next generation of embedded and distributed technologies will compound the problems through increased demand and diversity. This paper discusses the implications for the progression of current techniques into new methods for future software engineering of parallel systems. © 1995 IEEE.

关键词： Software engineering

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parallel polygon rendering on the graphics computer VC-1 1

Parallel polygon rendering on the graphics computer VC-1

引用

1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Kunii, Tosiyasu L. Nishimura, Satoshi School of Computer Science and Engineering University of Aizu Fukushima965-80 Japan

ISBN: (纸本)081867038X

This paper describes a parallel polygon rendering method on the graphics computer VC-1. The architecture of the VC-1 is a loosely-coupled array of general-purpose processors, each of which is equipped with a local frame buffer. The contents of the local frame buffers are merged into one in real time considering the visibility control based on screen depth. In our polygon rendering method, polygons are distributed among the processors and each processor independently computes the image of the assigned polygons using the Z-buffer method. To achieve load balancing, a technique called adaptive parallel rasterization is developed. The adaptive parallel rasterization automatically selects the appropriate parallelizing approach according to the estimated size of polygons displayed on the screen. The measured rendering performance of VC-1 using this polygon rendering method is shown. © 1995 IEEE.

关键词： Rasterization

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Constructing parallel implementations with algebraic programming tools 1

Constructing parallel implementations with algebraic program...

引用

1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Doroshenko, A.E. Godlevsky, A.B. Recursive Computers Department Glushkov Institute of Cybernetics Ukrainian Academy of Sciences Kiev252187 Ukraine Digital Automata Theory Department Glushkov Institute of cybernetics Ukrainian Academy of Sciences Kiev252187 Ukraine

ISBN: (纸本)081867038X

An approach to declarative construction of parallel implementations (dynamical parallelizers) for a general class of sequential imperative programs by means of the algebraic programming system APS is considered. It gives advantages of rapid prototyping and evolutionary development of efficient parallelizers. An operational model of a dynamical parallelizer in the form of transition system is constructed and major parts of its declarative implementation are described as systems of relations. Techniques for designing efficient parallelizers are presented and exemplified. © 1995 IEEE.

关键词： Algebra

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Design of high-performance massively parallel architectures under pin limitations and non-uniform propagation delay

Design of high-performance massively parallel architectures ...

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Yeh, Chi-Hsiang Parhami, Behrooz Univ of California Santa Barbara United States

Inter-module bandwidth is one of the major constraints on the performance of current and future parallel systems. In this paper, we propose and evaluate several high-performance bus-based parallel architectures, including bus-based cyclic networks (BCNs) and quotient cyclic networks (BQCNs), which are particularly efficient in view of their respective inter-module communication patterns. The inter-cluster connection in a BCN is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degree of a basic BCN is 3;while those of BQCNs and enhanced BCNs can vary from a small constant (e.g., 2) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. A variety of algorithms can be performed efficiently on these networks, thus proving the versatility of BCNs and BQCNs.

关键词： parallel processing systems

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architecture-independent workload characterization model for parallel computer architectures

Architecture-independent workload characterization model for...

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Meajil, Abdullah I. El-Ghazawi, Tarek Sterling, Thomas George Washington Univ Washington United States

In this paper, a model is presented for representing and comparing workloads, based on the way they would exercise parallel machines. This workload characterization is derived from parallel instruction centroid and parallel workload similarity. The centroid is a simple measure that aggregates average parallelism, instruction mix, and critical path length. When captured with abstracted information about communication requirements, the result is a powerful tool in understanding the requirements of workloads and their potential performance on target machines. The workload similarity is based on measuring the normalized Euclidean distance (ned) between workload centroids. It will be shown that this workload representation method outperforms comparable ones in accuracy, as well as in time and space requirements. Analysis of the NAS parallel Benchmarks and their performance is presented to demonstrate some of the applications, such as performance prediction with good accuracy, and insight provided by this model.

关键词： parallel processing systems

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Dynamic randomized simulation of hierarchical PRAMs on meshes 1

Dynamic randomized simulation of hierarchical PRAMs on meshe...

引用

1st aizu international symposium on parallel algorithms/architecture synthesis, AISPAS 1995

作者： Heywood, Todd Leopold, Claudia Department of Computer Science University of Edinburgh EdinburghEH93J2 United Kingdom Fakultat fur Mathematik und Informatik Friedrich-Schiller-Universitat Jena Jena07740 Germany

ISBN: (纸本)081867038X

The Hierarchical PRAM (H-PRAM) (T. Heywood, S. Ranka, 1992) model is a dynamically partitionable PRAM, which charges for communication and synchronization, and allows parallel algorithms to abstractly represent general locality. We show that the H-PRAM can be implemented efficiently on a two dimensional mesh. We use the Peano indexing scheme to hierarchically partition the mesh. Multiple subPRAMs of the H-PRAM are simulated on irregular submeshes. For an H-PRAM program of cost T, the overall CRCW H-PRAM simulation runs in time constant in T with high probability. The simulation is dynamic, i.e. it does not depend on prior knowledge of a program's specific hierarchical configuration, which may be data dependent. © 1995 IEEE.

关键词： parallel algorithms

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A parallel and fault-tolerant LAN with dual communication subnetworks

A parallel and fault-tolerant LAN with dual communication su...

引用

2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Wang, HQ Yin, ZL Wang, D Department of Computer and Information Science Harbin Engineering of Technology Harbin China

ISBN: (纸本)0818678704

In this paper a parallel and fault-tolerant LAN (P_FTLAN) with dual communication subnetworks is presented to improve LANs' reliability. Its function modes, technical characters, hardware and software architectures and some key, implementation techniques, such as logical addresses and parallel mechanisms, are described in details. Our prototype system and analyzing results suggest that the scheme presented in the paper not only provides an effective approach to high reliable LANs, but also can improve their performance greatly.

关键词： parallel P_FTLAN LAN reliability fault-tolerant dual communication subnetworks

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Efficient processor allocation algorithm using two-dimensional packing

Efficient processor allocation algorithm using two-dimension...

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Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Hwang, Injae Chungbuk Natl Univ Chungbuk Korea Republic of

Mesh is one of the most widely used interconnection networks for multiprocessor systems. In this paper, we propose an approach to partition a given mesh into m submeshes which can be allocated to m tasks with grid structures. We adapt two-dimensional packing to solve the submesh allocation problem. Due to the intractability of the two-dimensional packing problem, finding an optimal solution is computationally infeasible. We develop an efficient heuristic packing algorithm called TP-heuristic. Allocating a submesh to each task is achieved using the results of packing. We propose two different methods called uniform scaling and non-uniform scaling. Experiments were carried out to test the accuracy of solutions provided by our allocation algorithm.

关键词： parallel processing systems

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parallel algorithm for k-minimum spanning trees

Parallel algorithm for k-minimum spanning trees

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Ma, Jun Iwama, Kazuo Gu, Qian-Ping Shandong Univ Jinan Jinan China

A parallel algorithm to find k, 2 &le k &le nn-2, spanning trees from a connected, weighted and undirected graph G(V, E, W) in the order of increasing weight is presented. It runs in O(T(n) + k log n) time with O(n2/log n) processors on a CREW PRAM, where n = /V/, m = /E/ and T(n), O(log n) &le T(n) &le O(log2 n), is the time of the fastest parallel algorithms to find a minimum spanning tree of G on a CREW PRAM with no more than O(n2/log n) processors. Since T(n) = O(log2 n) for the time being, this result shows that to find k minimum spanning trees can be done in the same time bound as to find just one when k &le O(log n) on a CREW PRAM.

关键词： parallel algorithms

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