The MPEG-4 audio standard provides a toolset for audio synthesis and audio processing, i.e. structured audio (SA). SA permits one to describe algorithms through its Structured Audio Orchestra Language (SAOL) programmi...
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The MPEG-4 audio standard provides a toolset for audio synthesis and audio processing, i.e. structured audio (SA). SA permits one to describe algorithms through its Structured Audio Orchestra Language (SAOL) programming language. Unlike some other languages of the same type, SAOL has a sample-by-sample execution structure, and this makes particularly important the overhead computation in case of an interpreted decoder implementation. This paper describes the design of an efficient virtual architecture able to exploit the data level parallelism contained in many audio synthesis and processing algorithms and to consistently reduce the implementation overhead through a block-by-block execution.
The proceedings contains 47 papers. Topics discussed include memory performance and architecture, communication networks and routing, allocation and load balancing, algorithms and techniques, synchronization, communic...
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The proceedings contains 47 papers. Topics discussed include memory performance and architecture, communication networks and routing, allocation and load balancing, algorithms and techniques, synchronization, communication and prefetching, tools, environment and techniques, simulation, tools and techniques, parallel systems and algorithms.
We propose a new topology for multicomputer networks: parametrically described, regular, and based on semigroups (PRS) networks (or R/sub s/(N, v, g) graphs with the order N, the degree v, the girth g, and the number ...
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ISBN:
(纸本)0769509363
We propose a new topology for multicomputer networks: parametrically described, regular, and based on semigroups (PRS) networks (or R/sub s/(N, v, g) graphs with the order N, the degree v, the girth g, and the number of equivalence classes s). Many classes of networks such as hypercubes, circulants, cube-connected cycles, etc. are shown to be special cases of the proposed network. We explore the basic structure, topological properties, optimization of parameters and synthesis of optimal networks having the minimal diameter for the given parameters of the graph. Correspondingly, we examine the optimal characteristics with respect to transit delays and structural survival in such networks. The PRS networks reaching the lower bounds on the diameter were synthesized. In some cases, we found that the new network has a better diameter than classes of networks described in the literature provided they have the same vertex and edge complexity.
Application domain specific processors are becoming more and more appealing because of their peculiar feature of flexibility in terms of number of algorithms which one single architecture can execute and also in terms...
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Application domain specific processors are becoming more and more appealing because of their peculiar feature of flexibility in terms of number of algorithms which one single architecture can execute and also in terms of the possible computational improvement due to the increase of parallelism. The specific domain chosen is the family of Jacobi algorithms which are often used in the field of adaptative beamforming of radar signals. The architecture chosen should be weakly programmable. The idea is to derive in a systematic way a control program to be downloaded on a simulator of the processor to obtain quantitative information about the performance on the execution of every algorithm. Moreover some techniques to improve, from a qualitative point of view, the parallelization of execution are applied, suggested by the particular structure of the Jacobi algorithms.
This paper presents an integrated design system called SPARCS (synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) for automatically partitioning and synthesizing designs for reconfigurable board...
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ISBN:
(纸本)3540643591
This paper presents an integrated design system called SPARCS (synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) for automatically partitioning and synthesizing designs for reconfigurable boards with multiple field-programmable devices (FPGAs). The SPARCS system accepts design specifications at the behavior level, in the form of task graphs. The system contains a temporal partitioning tool to temporally divide and schedule the tasks on the reconfigurable architecture, a spatial partitioning tool to map the tasks to individual FPGAs, and a high-level synthesis tool to synthesize efficient register-transfer level designs for each set of tasks destined to be downloaded on each FPGA. Commercial logic and layout synthesis tools are used to complete logic synthesis, placement, and routing for each FPGA design segment. A distinguishing feature of the SPARCS system is the tight integration of the partitioning and synthesis tools to accurately predict and control design performance and resource utilizations. This paper presents an overview of SPARCS and the various algorithms used in the system, along with a brief description of how a JPEG-like image compression algorithm is mapped to a multi-FPGA board using SPARCS.
The proceedings contain 42 papers. The topics discussed include: improvement of duplication scheduling heuristic algorithm with nonstrict triggering of program graph nodes;cohesion : an efficient distributed shared me...
ISBN:
(纸本)081867038X
The proceedings contain 42 papers. The topics discussed include: improvement of duplication scheduling heuristic algorithm with nonstrict triggering of program graph nodes;cohesion : an efficient distributed shared memory system supporting multiple memory consistency models;supercompilers for massively parallelarchitectures;investigation of some hardware accelerators for relational algebra operations;implementing higher-order gamma on MasPar: a case study;a framework for visual parallel programming;parallelizing a PDE solver: experiences with PISCES-MP;efficient scalable mesh algorithms for merging, sorting and selection;and constructing parallel implement at ions with algebraic programming tools.
A parallel distributed scheme is presented for coding random patterns generated via iteration of contraction mappings. The scheme is implemented by a decentralized computational process an distributed parameter system...
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ISBN:
(纸本)0818678704
A parallel distributed scheme is presented for coding random patterns generated via iteration of contraction mappings. The scheme is implemented by a decentralized computational process an distributed parameter system. The distributed parameter system generates a representation of missing probability for attractor as the basis of design of contraction mappings. The local minimals of missing probability is extracted and aggregated as the decentralized representation of contraction mappings. The coding scheme is verified through computer simulation.
A new parallel algorithm for Householder bidiagonalization on parallel computers with dynamic ring architecture is presented. The Householder bidiagonalization is the core for singular value decomposition (SVD) which ...
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ISBN:
(纸本)0818678704
A new parallel algorithm for Householder bidiagonalization on parallel computers with dynamic ring architecture is presented. The Householder bidiagonalization is the core for singular value decomposition (SVD) which has been found to be very useful as an analytical tool in the presence of roundoff error and inexact data. Two-sided Householder reduction/expansion technique is applied for bidiagonalization. Innovative systolic-like communication techniques are proposed which eliminate the need for computing explicitly the transpose of the matrix. The experimental study on CM-5 shows that the parallel algorithm developed in this paper achieves high speedup for large matrices.
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