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共 162 条记录，以下是71-80 订阅

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A parallel and fault-tolerant LAN with dual communication subnetworks

A parallel and fault-tolerant LAN with dual communication su...

引用

2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Wang, HQ Yin, ZL Wang, D Department of Computer and Information Science Harbin Engineering of Technology Harbin China

ISBN: (纸本)0818678704

In this paper a parallel and fault-tolerant LAN (P_FTLAN) with dual communication subnetworks is presented to improve LANs' reliability. Its function modes, technical characters, hardware and software architectures and some key, implementation techniques, such as logical addresses and parallel mechanisms, are described in details. Our prototype system and analyzing results suggest that the scheme presented in the paper not only provides an effective approach to high reliable LANs, but also can improve their performance greatly.

关键词： parallel P_FTLAN LAN reliability fault-tolerant dual communication subnetworks

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Efficient processor allocation algorithm using two-dimensional packing

Efficient processor allocation algorithm using two-dimension...

引用

Proceedings of the 1997 2nd aizu international symposium on parallel algorithms/architecture synthesis

作者： Hwang, Injae Chungbuk Natl Univ Chungbuk Korea Republic of

Mesh is one of the most widely used interconnection networks for multiprocessor systems. In this paper, we propose an approach to partition a given mesh into m submeshes which can be allocated to m tasks with grid structures. We adapt two-dimensional packing to solve the submesh allocation problem. Due to the intractability of the two-dimensional packing problem, finding an optimal solution is computationally infeasible. We develop an efficient heuristic packing algorithm called TP-heuristic. Allocating a submesh to each task is achieved using the results of packing. We propose two different methods called uniform scaling and non-uniform scaling. Experiments were carried out to test the accuracy of solutions provided by our allocation algorithm.

关键词： parallel processing systems

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parallel genetic algorithms for communication network design

Parallel genetic algorithms for communication network design

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： Runhe Huang Jianhua Ma T.L. Kunii E. Tsuboi University of Aizu Japan

This paper is devoted to developing a genetic algorithm for a communication network design that minimizes total link cost, and subjects to some constraints like diameter and two-connectivity. Two parallel genetic algorithms on the level of partitioning requirements and the level of dividing population are proposed and implemented over a transputer based parallel network with various virtual network topologies. The ring-ring topology gives the best performance for the parallel genetic algorithm on the level of partitioning requirements, and the torus topology is the most suitable topology for the parallel genetic algorithm on the level of dividing population.

关键词： Genetic algorithms Communication networks Algorithm design and analysis Costs Network topology Random number generation Cities and towns Partitioning algorithms Optical fiber communication Telecommunication traffic

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Global synchronization of asynchronous arrays

Global synchronization of asynchronous arrays

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： V. Varshavsky V. Marakhovsky University of Aizu Aizu-Wakamatsu Japan

The problem of global synchronization in massively parallel systems is discussed for the level of models represented by asynchronous cellular automata arrays. Synchronization is called global if a given asynchronous automata array functions in logical time so that its behavior can be homomorphously mapped to the behavior of the prototype synchronous system in physical time. Our approach is decomposing the asynchronous array to synchro-stratum which acts as a distributed asynchronous clock and automata stratum whose automata have a construction similar to that of the synchronous prototype array automata. For various disciplines of prototype synchronization, the corresponding variants of synchro-stratum implementation for the asynchronous analogue are discussed.

关键词： Logic arrays Synchronization Clocks Hardware Automata Prototypes Software prototyping Signal processing Encyclopedias parallel programming

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Householder bidiagonalization on parallel computers with dynamic ring architecture

Householder bidiagonalization on parallel computers with dyn...

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： Shietung Peng S. Sedukhin I. Sedukhin University of Aizu Fukushima Japan Aizu Daigaku Aizuwakamatsu Fukushima JP R&D Group Hiwada Electronic Corporation Fukushima Japan

A parallel algorithm for Householder bidiagonalization on parallel computers with dynamic ring architecture is presented. The Householder bidiagonalization is the core for singular value decomposition (SVD) which has been found to be very useful as an analytical tool in the presence of roundoff error and inexact data. Two sided Householder reduction/expansion technique is applied for bidiagonalization. Innovative systolic like communication techniques are proposed which eliminate the need for computing explicitly the transpose of the matrix. The experimental study on the CM-5 shows that the parallel algorithm developed in the article achieves high speedup for large matrices.

关键词： Concurrent computing Computer architecture Research and development Lakes Very large scale integration parallel processing Power engineering and energy Computer applications Power engineering computing Eigenvalues and eigenfunctions

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A new parallel algorithm for the parentheses-matching problem

A new parallel algorithm for the parentheses-matching proble...

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： L. Bergogne C. Cerin Université de Picardie Jules-Verne Amiens France

The parentheses-matching problem is of crucial importance in the construction of expression tree in order to evaluate, for instance, arithmetic expressions. A new parallel algorithm is introduced in this paper to solve the parentheses-matching problem optimally (in O(log/sub 2/ n) parallel time with O(n/log/sub 2/ n) processors) on an EREW-PRAM model. An algorithm for an input string of n parentheses with a maximal nested level of log n is also presented.

关键词： parallel algorithms Phase change random access memory Arithmetic Formal languages Data structures Tree data structures Calculus Impedance matching

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An architecture based on the memory mapped node addressing in reconfigurable interconnection network

An architecture based on the memory mapped node addressing i...

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aizu international symposium on parallel algorithms/architecture synthesis

作者： T. Ikedo J. Yamada Y. Nonoyama J. Kimura M. Yoshida Computer Architecture Laboratory University of Aizu Japan

The paper proposes an architecture for a scalable supercomputing machine, based on a distributed virtual shared memory system. The processing elements used in this system consist of an ASIC embedding 5 PEs, 20 floating point multipliers, 15 adders, and one divider and square root arithmetic unit in a single chip. The 5 PEs are interconnected with a complete graph. The reconfigurable architecture is designed for dynamic high performance applications like virtual reality or multimedia systems. One chip implements a cluster, and an intercluster network can be established through a multiple interconnection network of these chips. It has 3.0 Gflops/chip as hardware peak performance, and can be scaled by an optical link via a specified router.

关键词： Multiprocessor interconnection networks Computer architecture parallel processing Hardware Protocols Costs Virtual reality Laboratories Cities and towns Application specific integrated circuits

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Program synthesis from film specifications

Program synthesis from film specifications

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： N. Mirenkov T. Mirenkova University of Aizu Fukushima Japan Aizu Daigaku Aizuwakamatsu Fukushima JP

This paper presents an outline of our strategy for program synthesis within the VIM film technology where special-purpose animation films are used as a new type of abstraction. To specify an algorithm/method the user develops his/her own film. New films are created through cutting, editing and other click operations by combining and merging component films. These operations predefine transformation rules to be performed with templates related to the system films. These templates are hand-made programs or files of a few hierarchical levels taking into account various kinds of programming know-how and techniques for the efficient implementation of computation on a target computer system. The program synthesis is performed by sequential transformations of the above-mentioned programs and files.

关键词： Cities and towns Electronic mail Animation Design methodology Algorithm design and analysis Graphics Timing Multimedia databases Data processing Knowledge acquisition

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Introducing parallelism in multimedia database systems

Introducing parallelism in multimedia database systems

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aizu international symposium on parallel algorithms/architecture synthesis

作者： G. Specht S. Zimmermann A. Clausnitzer Department of Computer Science Technische Universität München Munchen Germany

We discuss possibilities of parallelizing multimedia database systems, especially based on our experiences with our multimedia database system MultiMAP and our parallel database system MIDAS. We describe both initial systems in brief. Our main purpose is to examine when parallelism is of advantage and where sequential processing in multimedia databases is sufficient.

关键词： Multimedia databases Database systems parallel processing Relational databases Object oriented databases Multimedia systems Protection Object oriented modeling Computer science World Wide Web

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Instruction-level parallel processors-dynamic and static scheduling tradeoffs

Instruction-level parallel processors-dynamic and static sch...

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aizu international symposium on parallel algorithms/architecture synthesis

作者： K.W. Rudd M.J. Flynn Stanford University Computer Systems Laboratory USA

Recently, high performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These designs are complex and have frequently shown disappointing performance. A complementary approach is the use of static scheduling techniques to exploit the same parallelism. We describe some of the tradeoffs between the use of static and dynamic scheduling techniques and show that with appropriate scheduling, low complexity designs using only static scheduling have significant advantages over high complexity designs using dynamic scheduling in real systems.

关键词： Processor scheduling Dynamic scheduling Hardware Performance analysis Process design Delay VLIW Concurrent computing Laboratories Computer architecture

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