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共 162 条记录，以下是81-90 订阅

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Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs 20

Implementation of a programmable array processor architectur...

引用

20th IEEE international parallel and Distributed Processing symposium, IPDPS 2006

作者： Michailidis, Panagiotis D. Margaritis, Konstantinos G. Parallel and Distributed Processing Laboratory University of Macedonia Department of Applied Informatics 156 Egnatia str. 54006 Thessaloniki Greece

ISBN: (纸本)1424400546

Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don't care, complement and classes symbols. We also implement and evaluate the proposed architecture, on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 9-340 times faster than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024. © 2006 IEEE.

关键词： Computer architecture

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Discrete-event simulation of parallel machines

Discrete-event simulation of parallel machines

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aizu international symposium on parallel algorithms/architecture synthesis

作者： V. Lazarov R. Iliev Laboratory for Parallel and Distributed Processing Bulgarian Academy of Sciences Sofia Bulgaria

Presents a new approach for parallel machine simulation based on the discrete-event system specification (DEVS) formalism. Our simulation approach is directed toward parallel machine simulation at the concurrent threads level, and it is applicable for analysing the influence of internal algorithm/application concurrency on the performance characteristics of parallel machines. It uses as its modeling environment an abstraction of the parallel program's concurrent threads. The description of the modeled parallel machine is based on template models of the threads. We consider a program environment for discrete-event simulation of parallel computers based on our simulation approach. We also present some performance/utilization results from the simulation of a parallel database machine class, performed with our simulation environment.

关键词： Discrete event simulation parallel machines Yarn Computational modeling Analytical models Concurrent computing Discrete event systems Performance analysis Algorithm design and analysis Application software

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An efficient processor allocation algorithm using two-dimensional packing

An efficient processor allocation algorithm using two-dimens...

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aizu international symposium on parallel algorithms/architecture synthesis

作者： Injae Hwang Department of Computer Education Chungbuk National University South Korea

ISBN: (纸本)0818678704

The mesh is one of the most widely used interconnection networks for multiprocessor systems. We propose an approach to partition a given mesh into m submeshes which can be allocated to m tasks with grid structures. We adapt two dimensional packing to solve the submesh allocation problem. Due to the intractability of the two dimensional packing problem, finding an optimal solution is computationally infeasible. We develop an efficient heuristic packing algorithm called TP-heuristic. Allocating a submesh to each task is achieved using the results of packing. We propose two different methods called uniform scaling and non uniform scaling. Experiments were carried out to test the accuracy of solutions provided by our allocation algorithm.

关键词： Partitioning algorithms Hypercubes Shape Multiprocessing systems Multiprocessor interconnection networks Computer science education Heuristic algorithms Testing parallel processing Concurrent computing

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The stereo correspondence problem on a ring-based network

The stereo correspondence problem on a ring-based network

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： H.R. Arabnia Department of Computer Science 415 Graduate Studies Research Center University of Georgia Athens GA USA

A reconfigurable network called the "reconfigurable multi-ring network" (RMRN) is described. The RMRN is shown to be a truly scalable network in that each node in the network has a fixed degree of connectivity and the reconfiguration mechanism ensures a network diameter of O(log/sub 2/N) for an N-processor network. Basic message passing and reconfiguration primitives for the SIMD/SPMD RMRN are designed for use as building blocks for more complex parallel algorithms. The RMRN is shown to be a viable architecture for image processing and computer vision problems. As an example, a problem of stereo correspondence, known as the stereocorrelation operation, is addressed. Stereocorrelation is one of the most computationally intensive imaging tasks. It is used as a visualization tool in many applications, including remote sensing, geographic information systems and robot vision.

关键词： Stereo vision Message passing Algorithm design and analysis parallel algorithms Computer architecture Image processing Computer vision Visualization Application software Remote sensing

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The use of feedback in scheduling parallel computations

The use of feedback in scheduling parallel computations

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aizu international symposium on parallel algorithms/architecture synthesis

作者： R.D. Dietz T.L. Casavant M.S. Andersland T.A. Braun T.E. Scheetz Parallel Processing LaboratoryElectrical and Computer Engineering Department University of Iowa Iowa IA USA

Discusses the use of run-time feedback for optimizing the execution of parallel computations. Four levels of feedback are distinguished and the applicability and limitations of each are discussed. A two-part scheduling paradigm known as SEDIA (Static Exploration/Dynamic Instantiation and Activation) that addresses these limitations to perform robust scheduling in the presence of variant run-time behaviour is introduced. A key component of this scheduling paradigm is an abstract model of run-time information fidelity, which has evolved from our previous work in the area of trace recovery, employing control-theoretic concepts.

关键词： Feedback Processor scheduling Concurrent computing Optimal scheduling Runtime parallel processing Delay Robustness Laboratories Cities and towns

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Memory hierarchy design for Jetpipeline: to execute scalar and vector instructions in parallel

Memory hierarchy design for Jetpipeline: to execute scalar a...

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： T. Sasaki T. Nakaike K. Takano M. Katahira H. Kobayashi T. Nakamura Graduate School of Information Sciences University of Tohoku Sendai Japan

Superscalar and VLIW architectures are based on instruction level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, the paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.

关键词： Computer architecture parallel processing Dynamic scheduling Clocks Computer aided instruction Pipelines Processor scheduling System performance Computational modeling Business

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Efficient parallel and distributed topological sort algorithms

Efficient parallel and distributed topological sort algorith...

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aizu international symposium on parallel algorithms/architecture synthesis

作者： J. Ma K. Iwama T. Takaoka Qian-Ping Gu The Department of Computer Science and Communication Engineering Kyushu University Fukuoka Japan Department of Computer Scienc Ibaraki University Hitachi Japan Department of Computer Software University of Aizu Fukushima Japan DepartmentComputer Science Shandong University Jinan China

In this paper, we give efficient parallel and distributed algorithms for the topological sort problem on acyclic graphs with n vertices. Our parallel algorithm solves the problem on a CREW PRAM in O(log/sup 2/ n) time with O(M(n)/log n) processors, where M(n) denotes the number of processors needed to multiply two n/spl times/n integer matrices over the integer ring. The best known upper bound of M(n) is O(n/sup 2.376/). The parallel algorithm can also solve the problem on processor arrays with reconfigurable bus systems in O(1) time and O(n/sup 3/) processors. Our distributed algorithm solves the topological sort problem of an arbitrary asynchronous network with communication complexity O(n/sup 2/).

关键词： Phase change random access memory Upper bound Shortest path problem Computer science Distributed algorithms Software Computational modeling Distributed computing Complexity theory

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Direct execution simulation of mobile agent algorithms

Direct execution simulation of mobile agent algorithms

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international symposium on parallel and Distributed Processing and Applications (ISPA 2003)

作者： Cao, JN Li, XH King, S He, YX Hong Kong Polytech Univ Dept Comp Internet & Mobile Comp Lab Kowloon Hong Kong Peoples R China Wuhan Univ Parallel & Distributed Comp Lab Comp Sch Wuhan 430072 Hubei Peoples R China

ISBN: (纸本)3540405232

Mobile agent has been applied to develop the solutions for various kinds of parallel and distributed computing problems. However, performance evaluation of mobile agent algorithms remains a difficult task, mainly due to the characteristics of mobile agents such as distributed and asynchronous execution, autonomy and mobility. This paper proposes a general approach based on direct execution simulation for evaluating the performance of mobile agent algorithms by collecting and analyzing the information about the agents during their execution. We describe the proposed generic simulation model, named MADES, the architecture of a software environment based on MADES, and a prototype implementation. A mobile agent-based distributed load balancing algorithm is used for experiments with the prototype.

关键词： Mobile agents

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Block-SVD algorithms and their adaptation to hypercubes and rings

Block-SVD algorithms and their adaptation to hypercubes and ...

引用

aizu international symposium on parallel algorithms/architecture synthesis

作者： M. Vajtersic M. Becka Institute for Informatics Slovak Academy of Sciences Bratislava Slovakia

The paper presents parallel algorithms for efficient solution of the SVD (singular value decomposition) problem by the block two sided Jacobi method. It is shown how the method could be applied to MIMD computers with the hypercube and ring topology. Three types of orderings for solving SVD on block structured submatrices are analysed from the point of view of communication requirements and suitability for a parallel execution of the computational process, which is carried out on block columns of the matrix. All three orderings fit well to the hypercube topology. Two of them can be directly implemented also on rings. The optimality in parallelization of the method and data transfers has been achieved there within each sweep. For the third scheme, an efficient numbering of processor nodes is discussed. Computer results obtained on an Intel Paragon system are shown for a chosen ordering.

关键词： Hypercubes Jacobian matrices Topology Concurrent computing parallel processing Informatics parallel algorithms Singular value decomposition Convergence Load management

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A parallel algorithm for k-minimum spanning trees

A parallel algorithm for k-minimum spanning trees

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aizu international symposium on parallel algorithms/architecture synthesis

作者： Jun Ma K. Iwama Qian-Ping Gu Department of Computer Science Shandong University Jinan China Department of Computer Science and Communication Engineering Kyushu University Fukuoka Japan Department of Computer Software University of Aizu Wakamatsu Japan

ISBN: (纸本)0818678704

A parallel algorithm to find k, 2/spl les/k/spl les/n/sup n-2/, spanning trees from a connected, weighted and undirected graph C(V, E, W) in the order of increasing weight is presented. It runs in O(T(n)+klogn) time with O(n/sup 2//log n) processors on a CREW PRAM, where n=|V|, m=|E| and T(n), O(log n)/spl les/T(n)/spl les/O(log/sup 2/ n), is the time of the fastest parallel algorithms to find a minimum spanning tree of G on a CREW PRAM with no more than O(n/sup 2//log n) processors. Since T(n)=O(log/sup 2/ n) for the time being, this result shows that to find k minimum spanning trees can be done in the same time bound as to find just one when k/spl les/O(log n) on a CREW PRAM.

关键词： parallel algorithms Tree graphs Phase change random access memory Computer science Software Concrete Algorithm design and analysis Terminology

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