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IMPROVED parallel INTEGER SORTING WITHOUT CONCURRENT WRITING 3

IMPROVED PARALLEL INTEGER SORTING WITHOUT CONCURRENT WRITING

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3RD annual SYMP OF THE ASSOC FOR COMPUTING MACHINERY AND THE SOC FOR INDUSTRIAL AND APPLIED MATHEMATICS : DISCRETE algorithms

作者： ALBERS, S HAGERUP, T Graduiertentolleg Informatik Universität des Saarlandes Saarbrücken W-6600 Germany Max-Planck-Institut für Informatik Saarbrücken W-6600 Germany

We show that n integers in the range 1. n can be stably sorted on an EREW PRAM using O(log n)3/2(log log n)1/2) time, O(n (log n)1/2(log log n)1/2) operations and O(n) space. In addition, we are able to stably sort n ... 详细信息

ISBN: (纸本)089791466X

We show that n integers in the range 1. n can be stably sorted on an EREW PRAM using O(log n)^3/2(log log n)^1/2) time, O(n (log n)^1/2(log log n)^1/2) operations and O(n) space. In addition, we are able to stably sort n integers in the range 1. n on a deterministic CREW PRAM in O((log n)^3/2) time with O(n (log n)^1/2) operations and O(n) space and to stably sort n arbitrary integers on a randomized CREW PRAM within the same complexity bounds with high probability. In each case our algorithm is closer to optimality than all previous algorithms for the stated problem in the stated model, and our third result matches the operation count of the best known sequential algorithm. We also show that n integers in the range 1. m can be sorted in O((log n)²) time with O(n) operations on an EREW PRAM using a nonstandard word length of O(lognloglognlogm) bits, thereby greatly improving the upper bound on the word length necessary to sort integers with a linear time-processor product, even sequentially. Our algorithms were inspired by, and in one case directly use, the fusion trees recently introduced by Fredman and Willard.

关键词： Clustering algorithms

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Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations 21

Efficient, Distributed, and Non-Speculative Multi-Address At...

引用

54th annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Jose Gomez-Hernandez, Eduardo Cebrian, Juan M. Titos-Gil, Ruben Kaxiras, Stefanos Ros, Alberto Univ Murcia Dept Comp Engn Murcia Spain Uppsala Univ Dept Informat Technol Uppsala Sweden

ISBN: (纸本)9781450385572

Critical sections that read, modify, and write (RMW) a small set of addresses are common in parallel applications and concurrent data structures. However, to escape from the intricacies of finegrained locks, which require reasoning about all possible thread interleavings, programmers often resort to coarse-grained locks to ensure atomicity. This results in atomic protection of a much larger set of potentially conflicting addresses, and, consequently, increased lock contention and unneeded serialization. As many before us have observed, these problems would be solved if only general RMW multi-address atomic operations were available, but current proposals are impractical because of deadlock scenarios that appear due to resource limitations. Alternatively, transactional memory can detect conflicts at run-time aiming to maximize concurrency, but it has significant overheads in highly-contended critical sections. In this work, we propose multi-address atomic operations (MAD atomics). MADatomics achieve complexity-effective, non-speculative, non-deadlocking, fine-grained locking for multiple addresses, relying solely on the coherence protocol and a predetermined locking order. Unlike prior works, MAD atomics address the challenge of enabling atomic modification over a set of cachelines with arbitrary addresses, simultaneously locking all of them while sidestepping deadlock. MAD atomics only require a small storage per core (around 68 bytes), while significantly outperforming typical lock implementations. Indeed, our evaluation using gem5-20 shows that MAD atomics can improve performance by up to 18x (3.4x, on average, for the applications and concurrent data structures evaluated in this work) over a baseline implemented with locks running on 16 cores. More importantly, the improvement still reaches 2.7x, on average, compared to an Intel hardware transactional memory implementation running on 16 cores.

关键词： Multi-core architectures synchronization critical sections atomicity multi-address atomics

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Efficient discovery of loop nests in execution traces

Efficient discovery of loop nests in execution traces

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International symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

作者： Xu, Qiang Subhlok, Jaspal Hammen, Nathaniel CGGVeritas Inc. United States Department of Computer Science University of Houston United States

ISBN: (纸本)9780769541976

Execution and communication traces are central to performance modeling and analysis. Since the traces can be very long, meaningful compression and extraction of representative behavior is important. Commonly used compression procedures identify repeating patterns in sections of the input string and replace each instance with a representative symbol. This can prevent the identification of long repeating sequences corresponding to outer loops in a trace. This paper introduces and analyzes a framework for identifying the maximal loop nest from a trace. The discovery of loop nests makes construction of compressed representative traces straightforward. The paper also introduces a greedy algorithm for fast "near optimal" loop nest discovery with well defined bounds. Results of compressing MPI communication traces of NAS parallel benchmarks show that both algorithms identified the basic loop structures correctly. The greedy algorithm was also very efficient with an average processing time of 16.5 seconds for an average trace length of 71695 MPI events. © 2010 IEEE.

关键词： MPI communication traces NAS parallel benchmarks Trace compression application program interfaces execution traces greedy algorithm greedy algorithms loop discovery loop structures message passing near optimal loop nest discovery performance modeling program control structures repeating patterns repeating sequences

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parallel retrograde analysis on different architecture

Parallel retrograde analysis on different architecture

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10th annual IEEE International symposium on High Performance Distributed Computing

作者： Wu, R Beal, DF HP Laboratories Hewlett-Packard Company Palo Alto CA United States

ISBN: (纸本)0769512968

Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. This paper looks at successful applications to games, the challenges ahead, and the modifications that are required to utilize distributed hardware. The power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 109 states in a few hours on a standard personal computer Bigger problems need more powerful computers, or take much longer to solve, or are simply out of reach of today's technologies, Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. There are today three main architectures available for doing parallel retrograde analysis: namely Symmetric Multiprocessor systems, High-speed network based distributed systems, and Internet based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. These examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

关键词： Distributed computer systems

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Design and Tool Flow of IBM's TrueNorth: An Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons 16

Design and Tool Flow of IBM's TrueNorth: An Ultra-Low Power ...

引用

acm International symposium on Physical Design (ISPD)

作者： Akopyan, Filipp A. IBM Corp Armonk NY 10504 USA

ISBN: (纸本)9781450340397

Developing scalable real-time systems that can simultaneously process massive amounts of noisy multi-sensory data, while being energy efficient, is a dominant challenge in the new era of cognitive computing. Low-power, flexible neurosynaptic architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65mW brain-inspired processor that implements a non-von Neumann, parallel, distributed, event-driven, modular, scalable, defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software. Given that the TrueNorth architecture breaks path with prevailing architectures, conventional tool flows could not be used for the design. Therefore, we developed a novel design methodology that includes mixed asynchronous-synchronous circuits, interfaces, and a complete tool flow for building an event-driven, low-power neurosynaptic chip. Further, we have adapted existing VLSI CAD placement tools for mapping logical neural networks to the physical core locations on the TrueNorth chip to reduce the network's communication energy. The TrueNorth chip's low power consumption is ideal for use not only in large-scale computationally intensive applications, but also for embedded battery-powered mobile applications. The chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. We have successfully demonstrated the use of TrueNorth chips in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower power than the same algorithms run on von Neumann architectures.

关键词： Asynchronous circuits asynchronous communication design automation design methodology image recognition logic design low-power electronics neural networks neural network hardware neuromorphics parallel architectures real-time systems synchronous circuits very large-scale integration custom tool flow

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Introducing the hydra parallel programming system 06

Introducing the hydra parallel programming system

引用

Proceedings of the eighteenth annual acm symposium on parallelism in algorithms and architectures

作者： Franklin E. Powers Gita Alaghband University of Colorado at Denver and Health & Sciences Center Denver CO

ISBN: (纸本)9781595934529

Hydra PPS is a collection of annotations, classes, a runtime, and a compiler designed to provide Java programmers with a fairly simple method of producing programs for Symmetric Multiprocessing (SMP) architectures. This paper introduces the basics of this new system including the basic constructs for this new programming language and the relationship between the Java VM, the compiler, the runtime, and the parallel program. Hydra will exploit parallelism when the underlying architecture supports it and will run as normal sequential Java program when the architecture does not have support for parallelism. parallelism is expressed through events in Hydra, it is easy to use, and programs run efficiently on parallel architectures.

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parallel processing of biological sequence comparison algorithms

Parallel processing of biological sequence comparison algori...

引用

Proceedings - Twelfth annual symposium on Computer Applications in Medical Care

作者： Core, Nolan G. Edmiston, Elizabeth W. Saltz, Joel H. Smith, Roger M. Yale Univ Sch of Medicine New Haven CT USA

ISBN: (纸本)0818608811

Methods of implementing biological (DNA or protein) sequence-compromise algorthms on the Intel iPSC/1 hypercube and the CM-1 microprocessor, machines which have very different architectures, are demonstrated. The CM-I is significantly faster when the sizes of the sequences to be compared are relatively large. However, the small memory for each of the CM-I processors prevents the storage of the necessary information for the traceback procedure. Consequently, the traceback must be performed in more than one pass. The Intel iPSC/1 hypercube, on the other hand, has more than enough storage for the traceback procedure, but is slower for larger size sequences because it has two orders of magnitude fewer processors han the CM-I. However, the Intel iPSC/2 hypercube is faster by a factor of four to five, and the CM-II has more memory.

关键词： Biomedical Engineering

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Fault-tolerant wafer-scale architectures for VLSI 9

Fault-tolerant wafer-scale architectures for VLSI

引用

9th annual symposium on Computer Architecture, ISCA 1982

作者： Fussell, Donald Varman, Peter University of Texas at Austin AustinTX78712 United States

The basic problem which limits both yields and chip sizes is the fact that circuits created using current design techniques will not function correctly in the presence of even a single flaw of sufficient size anywhere on the chip. In this work we examine the problem of constructing chips up to the size of a wafer which operate correctly despite the presence of such flaws. This can be accomplished by building on the wafer a nearest-neighbor network of small, independent, asynchronously communicating modules. A specific algorithm to be performed by the wafer is then mapped onto a fault-free subgraph of the network. We are interested in algorithms which map naturally onto a linear array of identical processors. Construction of fault-tolerant implementations of these algorithms is addressed in two contexts. First we consider the general problem of finding a fault-free subgraph of the host network which is isomorphic to the linear array required to solve a problem. We then examine ways to tailor a specific, known algorithm to the fault-tolerant context. © 1982 IEEE.

关键词： Fault tolerance

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Modeling parallel bandwidth: local vs. global restrictions 97

Modeling parallel bandwidth: local vs. global restrictions

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Proceedings of the ninth annual acm symposium on parallel algorithms and architectures

作者： Micah Adler Phillip B. Gibbons Vijaya Ramachandran Yossi Matias Heinz Nixdorf Institute Room F1-119 Fürstenallee 11 D-33102 Paderborn Germany Bell Laboratories Lucent Technologies 600 Mountain Ave. Murray Hill NJ Dept. of Computer Sciences University of Texas at Austin Austin TX

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Combining tentative and definite executions for very fast i)ependable parallel computing 23

Combining tentative and definite executions for very fast i)...

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23rd annual acm symposium on Theory of Computing, STOC 1991

作者： Kedem, Z.M. Palem, K.V. Raghunathan, A. Spirakis, P.G. Ecole des Hautes Etudes en Jniormatique Université René Descartes 45 rue des Saints-Pares Paris75006 France Department of Computer Science New York University 251 Mercer St New YorkNY10012-1185 United States Research Center and the Institute for Advanced Computer Studies University of Maryland. IBM Research Division T. 3. Watson Research Center P. 0. Box 704 Yorktown HeightNY10598 United States Computer Science Division University of California DavisCA95616 United States Computer Technology Institute Patras University P. 0. Box 1122 Patras26110 Greece

ISBN: (纸本)0897913973

We present a general and efficient strategy for computing mtustly on unreliable parallel machines. The model of a parallel machine that we use is a CRCW PRAM with dynamic resource fluctuations: processors can fail during the computation, and may possibly bc restored later. We first introduce the notions of dejinite and tentatitie algorithms for executing a single parallel step of an ideal parallel machine on the unreliable machine. A definite algorithm is one that guarantees a correct execution of a step, while a tentative algorithm is one that is "highly likely" to produce a correct execution of a step on the unreliable machine. We show that any definite execution of one step requires Cl(log n) time on an∗processor unreliable machine, even if all the processors functioned perfectly, This implies an l(log n) slowdown for executing any non-Trivial program on the unreliable machine, provided only definite executions are used. We get around this overhead by combining tentative and definite execution schemes appropriately, to derive correct and efllcient robust executions for arbitrary PRAM programs, with expected amortized slowdown of only 0(1) for a variety of reasonable failure models. We adeve this by using a tentative algorithm to execute each of the program's steps, while using a definite algorithm to audit the execution at selected points. If the audit does not certify the execution as correct, then the execution is rolled back to a previous audit point and restarted from there. In contrast to this work, all previous results required a slowdown of Cl(log n), since they used definite algorithms only. © 1991 acm.

关键词： parallel processing systems

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