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A no-busy-wait balanced tree parallel algorithmic paradigm 00

A no-busy-wait balanced tree parallel algorithmic paradigm

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Proceedings of the twelfth annual acm symposium on parallel algorithms and architectures

作者： Uzi Vishkin University of Maryland

ISBN: (纸本)9781581131857

Suppose that a parallel algorithm can include any number of parallel threads. Each thread can proceed without ever having to busy wait to another thread. A thread can proceed till its termination, but no new threads can be formed. What kind of problems can such restrictive algorithms solve and still be competitive in the total number of operations they perform with the fastest serial algorithm for the same problem?Intrigued by this informal question, we considered one of the most elementary parallel algorithmic paradigms, that of balanced binary trees. The main contribution of this paper is a new balanced (not necessarily binary) tree no-busy-wait paradigm for parallel algorithms; applications of the basic paradigm to two problems are presented: building heaps, and executing parallel tree contraction (assuming a preparatory stage); the latter is known to be applicable to evaluating a family of general arithmetic *** putting things in context, we also discuss our “PRAM-on-chip” vision (actually a small update to it), presented at SPAA98.

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A quantitative approach for teaching parallel computing 92

A quantitative approach for teaching parallel computing

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Proceedings of the twenty-third SIGCSE technical symposium on Computer science education

作者： E. Luque R. Suppi J. Sorribes Department d'Informàtica Universitat Autònoma de Barcelona 08193-Bellaterra Barcelona Spain

ISBN: (纸本)9780897914680

parallel computing teaching has an important difficulty, there are few tools to directly learn the behavior of the parallel algorithms and the parallel architectures. Normally the student is formed to think in sequential algorithms running in sequential machines. We present PSEE, a tool to reduce the gap between the basic concepts and its utilization. PSEE is an integrated and interactive graphic environment which allows to simulate and evaluate the performance of parallel algorithms in parallel architectures. PSEE permits to manage the main characteristic parameters involved in the system in order to show the tuning grade of the algorithm/architecture couple. PSEE includes a graphic editor for algorithms and architectures in modelled form, an interactive simulator to run (simulate) the algorithm on the architecture and a performance evaluation instrument.

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Software pipelining loops with conditional branches 29

Software pipelining loops with conditional branches

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： M.G. Stoodley C.G. Lee Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada

ISBN: (纸本)9780818676413

Software pipelining is an aggressive scheduling technique that generates efficient code for loops and is particularly effective for VLIW architectures. Few software pipelining algorithms, however, are able to efficiently schedule loops that contain conditional branches. We have developed an algorithm we call All Paths Pipelining (APP) that addresses this shortcoming of software pipelining. APP is designed to achieve optimal or near-optimal performance for any run of iterations while providing efficient code for transitioning between runs. A run is the execution of consecutive iterations that all execute the same path through a loop. APP accomplishes this by using techniques from modulo scheduling and kernel recognition algorithms, the two main approaches for software pipelining loops. We have implemented the APP algorithm in our research compiler and have evaluated its performance by executing its generated code on a VLIW instruction-set simulator. For a processor with five heterogeneous functional units, APP is able to add another 1% to 23% increase in performance over basic software pipelining by effectively pipelining loops with conditional branches.

关键词： Pipeline processing VLIW Scheduling algorithm Processor scheduling Computer architecture Software algorithms Hardware parallel processing Kernel Microprocessors

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Dynamic scheduling on parallel machines

Dynamic scheduling on parallel machines

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annual IEEE symposium on Foundations of Computer Science

作者： S. Feldmann J. Sgall S.-H. Teng School of Computer Science Carnegie Mellon University Pittsburgh PA USA Xerox-PARC Palo Alto CA USA

The problem of online job scheduling on various parallel architectures is studied. An O((log log n)/sup 1/2/)-competitive algorithm for online dynamic scheduling on an n*n mesh is given. It is proved that this algorithm is optimal up to a constant factor. The algorithm is not greedy, and the lower bound proof shows that no greedy-like algorithm can be very good. The upper bound result can be generalized to any fixed-dimensional meshes. Competitive scheduling algorithms for other architectures are given.< >

关键词： Dynamic scheduling parallel machines Scheduling algorithm parallel architectures Processor scheduling Phase change random access memory Computer science Heuristic algorithms Upper bound Time sharing computer systems

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Safe Nondeterminism in a Deterministic-by-Default parallel Language 11

Safe Nondeterminism in a Deterministic-by-Default Parallel L...

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38th symposium on Principles of Programming Languages

作者： Bocchino, Robert L., Jr. Heumann, Stephen Honarmand, Nima Adve, Sarita V. Adve, Vikram S. Welc, Adam Shpeisman, Tatiana Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450304900

A number of deterministic parallel programming models with strong safety guarantees are emerging, but similar support for non-deterministic algorithms, such as branch and bound search, remains an open question. We present a language together with a type and effect system that supports nondeterministic computations with a deterministic-by-default guarantee: nondeterminism must be explicitly requested via special parallel constructs (marked nd), and any deterministic construct that does not execute any nd construct has deterministic input-output behavior. Moreover, deterministic parallel constructs are always equivalent to a sequential composition of their constituent tasks, even if they enclose, or are enclosed by, nd constructs. Finally, in the execution of nd constructs, interference may occur only between pairs of accesses guarded by atomic statements, so then;are no data races, either between atomic statements and unguarded accesses (strong isolation) or between pairs of unguarded access (stronger than strong isolation alone). We enforce the guarantees at compile time with modular checking using novel,extensions to a previously described effect system. Our effect system extensions also enable the compiler to remove unnecessary transactional synchronization. We provide a static semantics, dynamic semantics, and a complete proof of soundness for the language;both with, and without the barrier removal feature. An experimental evaluation shows that our language can achieve good scalability for realistic parallel algorithms, and that the barrier removal techniques provide significant performance gains.

关键词： strong isolation transactional memory determinism atomicity effects parallel programming languages data race freedom tranasctions effect systems nondeterminism atomic sections

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ParGeo: A Library for parallel Computational Geometry 30

ParGeo: A Library for Parallel Computational Geometry

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30th annual European symposium on algorithms, ESA 2022

作者： Wang, Yiqiu Yesantharao, Rahul Yu, Shangdi Dhulipala, Laxman Gu, Yan Shun, Julian CSAIL MIT CambridgeMA United States University of Maryland College ParkMD United States University of California RiversideCA United States

ISBN: (纸本)9783959772471

This paper presents ParGeo, a multicore library for computational geometry. ParGeo contains modules for fundamental tasks including kd-tree based spatial search, spatial graph generation, and algorithms in computational geometry. We focus on three new algorithmic contributions provided in the library. First, we present a new parallel convex hull algorithm based on a reservation technique to enable parallel modifications to the hull. We also provide the first parallel implementations of the randomized incremental convex hull algorithm as well as a divide-and-conquer convex hull algorithm in R3. Second, for the smallest enclosing ball problem, we propose a new sampling-based algorithm to quickly reduce the size of the data set. We also provide the first parallel implementation of Welzl's classic algorithm for smallest enclosing ball. Third, we present the BDL-tree, a parallel batch-dynamic kd-tree that allows for efficient parallel updates and k-NN queries over dynamically changing point sets. BDL-trees consist of a log-structured set of kd-trees which can be used to efficiently insert, delete, and query batches of points in parallel. On 36 cores with two-way hyper-threading, our fastest convex hull algorithm achieves up to 44.7x self-relative parallel speedup and up to 559x speedup against the best existing sequential implementation. Our smallest enclosing ball algorithm using our sampling-based algorithm achieves up to 27.1x self-relative parallel speedup and up to 178x speedup against the best existing sequential implementation. Our implementation of the BDL-tree achieves self-relative parallel speedup of up to 46.1x. Across all of the algorithms in ParGeo, we achieve self-relative parallel speedup of 8.1-46.61x. © 2022 Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing. All rights reserved.

关键词： Computational geometry

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Sequential and parallel algorithms to find a K5 minor 92

Sequential and parallel algorithms to find a K5 minor

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Proceedings of the third annual acm-SIAM symposium on Discrete algorithms

作者： André Kézdy Patrick McGuinness

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Online Scheduling with General Cost Functions 12

Online Scheduling with General Cost Functions

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annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： Sungjin Im Benjamin Moseley Kirk Pruhs Department of Computer Science University of Illinois Computer Science Department University of Pittsburgh

ISBN: (纸本)9781611972108

One obvious question is if there exists an online algorithm that is O(1)-competitive with speed less than two or not. To obtain such an algorithm (if exists), one must exploit the structure of cost functions. Our analysis can be extended to show that there exists an O(1)-speed O(1)-competitive algorithm on identical parallel machines.

关键词： Cost functions parallel machines There exists algorithms

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FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities

FPGA Architecture of Generalized Laguerre-Volterra MIMO Mode...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Li, Will X. Y. Cheung, Ray C. C. Zhang, Wei Chan, Rosa H. M. Song, Dong Berger, Theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Dept Biomed Engn Los Angeles CA 90007 USA

ISBN: (纸本)9780769543017

We present a parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component;a second stage containing a pre-threshold potential updating unit with an error approximation function component;and a third stage consisting of a gradient calculation unit. A flexible and efficient architecture that can accommodate different design speed requirements are generated. Simulation results are rigorously analyzed. A hardware IP library for versatile models and applications is proposed. The design runs on a Xilinx Virtex-6 FPGA and the processing core produces data samples at a maximum clock rate of 357MHz, which is 4.37 x 10(5) times faster than the corresponding software model running on an AMD Pheono 9750 Quad Core Processor. It occupies 216,766 LUTs, maximum 12 block-RAMs, and 2016 DSP-blocks.

关键词： AMD Pheono 9750 Quad Core Processor Arrays Biological system modeling Computational modeling FPGA architecture Field programmable gate arrays Hardware MIMO systems Software Xilinx Virtex-6 FPGA biology computing error approximation function component field programmable gate arrays generalized Laguerre-Volterra MIMO model gradient calculation unit multiply and accumulation component neural nets neural population spiking activities parallel architectures parallelized architecture pipeline processing pipelined architecture time-varying neural dynamics vector convolution

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Time-work tradeoffs for parallel graph algorithms 91

Time-work tradeoffs for parallel graph algorithms

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Proceedings of the second annual acm-SIAM symposium on Discrete algorithms

作者： Thomas H. Spencer Computer Science Department Rensselaer Polytechnic Institute

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